Datasheet
NAP AND POWERDOWN MODE CONTROL
GETTING DATA
Flexible Output Modes: A0 A1, and A2.
t
ACQ
t
D1
t
D8
16 17 18 19 20 1 2
CLK
HOLDX
EOC
CS
RD
A0
t
D9
t
D7
ADS8365
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.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008
B1, C0, and finally, C1 before reading A0 again. Data
from channel A0 are brought to the output first after a
In order to minimize power consumption when the
reset signal, or after powering up the device. The
ADS8365 is not in use, two low-power options are
third mode is a FIFO mode that is addressed with
available. Nap mode minimizes power without
(A2, A1, A0 = 111). Data of the channel that is
shutting down the biasing circuitry and internal
converted first is read first. So, if a particular channel
reference, allowing immediate recovery after it is
pair is most interesting and is converted more
disabled. It can be enabled by either the NAP pin
frequently (for example, to get a history of a particular
going high, or setting DB6 in the data register high.
channel pair), then there are three output registers
Enabling Powerdown mode results in lower power
per channel available to store data.
consumption than Nap mode, but requires a short
recovery period after disabling. It can only be enabled If all the output registers are filled up with unread
by setting DB5 in the data register high. data and new data from an additional conversion
must be latched in, then the oldest data is discarded.
If a read process is going on ( RD signal low) and new
data must be stored, then the ADS8365 waits until
the read process is finished ( RD signal going high)
before the new data gets latched into its output
The ADS8365 has three different output modes that
register. Again, with the ADD signal, it can be chosen
are selected with A2, A1, and A0. The A2, A1 and A0
whether the address should be added to the output
pins are held with a transparent latch that triggers on
data.
a falling edge of the RD pin negative-ANDed with the
New data is always written into the next available
CS pin (that is, if either RD or CS is low, the falling
register. At t
0
(see Figure 31 ), the reset deletes all the
edge of the other will latch A0-2).
existing data. At t
1
, the new data of the channels A0
When (A2, A1, A0) = 000 to 101, a particular channel
and A1 are put into registers 0 and 1. At t
2
, a dummy
can be directly addressed (see Table 1 and
read ( RD low) is performed to latch the address data
Figure 30 ). The channel address should be set at
correctly. At t
3
, the read process of channel A0 data
least 10ns (see Figure 30 , t
D9
) before the falling edge
is finished; therefore, these data are dumped and A1
of RD and should not change as long as RD is low. In
data are shifted to register 0. At t
4
, new data are
this standard address mode, ADD will be ignored, but
available, this time from channels B0, B1, C0, and
should be connected to either ground or supply.
C1. These data are written into the next available
registers (registers 1, 2, 3, and 4).
When (A2, A1, A0) = 110, the interface is running in a
cycle mode (see Figure 29 ). Here, data 7 down to
data 0 of channel A0 is read on the first RD signal,
and data 15 down to data 8 on the second as BYTE
is high. Then A1 on the second RD, followed by B0,
Figure 30. Timing for Reading Data
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