Datasheet
ADD Signal
Soft Trigger Mode
ADS8365
SBAS362C – AUGUST 2006 – REVISED MARCH 2008 ....................................................................................................................................................
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In the cycle and the FIFO mode, it might be desirable
If conversion timing between ADCs is not critical, Soft
to have address information with the 16-bit output
Trigger mode can allow all three HOLDX signals to
data. Therefore, ADD can be set high. In this case,
be triggered simultaneously. This simultaneous
two RD signals (or three readings if the part is
triggering can be done by tying all three HOLDX pins
operated with BYTE being high) are necessary to
high, and issuing a write ( CS and WR low) with the
read data of one channel, while the ADS8365
DB0, DB1, DB2, and DB7 bits low, and the reset bit
provides channel information on the first RD signal
(DB3) high. Writing a low to the reset bit (DB3) while
(see Table 2 and Table 3 ).
the RESET pin is high forces a device reset, and all
HOLDX signals that occur during that time are
ignored.
Signals NAP, ADD, A0, A1, A2, RESET, HOLDA,
The HOLDX signals start conversion automatically on
HOLDB, and HOLDC are accessible through the data
the next clock cycle. The format of the two words that
bus and control word. Bits NAP, ADD, A0, A1 and A2
can be written to the ADS8365 are shown in Table 4 .
are in an OR configuration with hardware pins. When
Bits DB5 and DB4 do not have corresponding
software configuration is used, these pins must be
hardware pins. Bit DB5 = 1 enables Powerdown
connected to ground. Conversely, the RESET,
mode. Bit DB4 = 1 inverts the MSB of the output
HOLDA, HOLDB, and HOLDC bits are in a NAND
data, putting the output data in two's complement
configuration with the hardware pins. When software
format. When DB4 is low, the data is in straight
configuration is used, these pins must be connected
binary format.
to BV
DD
.
Table 2. Overview of the Output Formats Depending on Mode When ADD = 0
ADD = 0 BYTE = 0 BYTE = 1
A2 A1 A0 1st RD 2nd RD 1st RD 2nd RD 3rd RD
000 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
001 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
010 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
011 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
100 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
101 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
110 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
111 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
Table 3. Overview of the Output Formats Depending on Mode When ADD = 1
ADD = 1 BYTE = 0 BYTE = 1
A2 A1 A0 1st RD 2nd RD 1st RD 2nd RD 3rd RD
000 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
001 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
010 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
011 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
100 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
101 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD
110 1000 0000 0000 DV A2 A1 A0 DB15...DB0 DV A2 A1 A0 DB3 DB2 DB0 DB7...DB0 DB15...DB8
111 1000 0000 0000 DV A2 A1 A0 DB15...DB0 DV A2 A1 A0 DB3 DB2 DB0 DB7...DB0 DB15...DB8
Table 4. Control Register Bits
DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB)
1 NAP PD Invert MSB ADD A2 A1 A0
0 X X X RESET HOLDA HOLDB HOLDC
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