Datasheet
Reading data ( RD and CS)
BYTE
CS
RD
BYTE
A0 A1 A1 B0 B0 B1 C0 C1 A0
HIGH
A0
LOW HIGH HIGHLOW LOW
D7 – D0
ADS8365
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.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008
CS being low tells the ADS8365 that the bus on the
board is assigned to the ADS8365. If an ADC shares
In general, the channel/data outputs are in tri-state.
a bus with digital gates, there is a possibility that
Both CS and RD must be low to enable these
digital (high-frequency) noise will be coupled into the
outputs. RD and CS must stay low together for at
ADC. If the bus is just used by the ADS8365, CS can
least 40ns (see Figure 1 , t
D6
) before the output data
be hardwired to ground. Reading data at the falling
are valid. RD must remain HIGH for at least 30ns
edge of one of the HOLDX signals might cause noise.
(see Figure 1 , t
W5
) before bringing it back low for a
subsequent read command.
The new data are latched into its output register 16.5
If there is only an 8-bit bus available on a board, then
clock cycles after the start of a conversion (next rising
BYTE can be set high (see Figure 29 ). In this case,
edge of clock after the falling edge of HOLDX). Even
the lower eight bits can be read at the output pins
if the ADS8365 is forced to wait until the read
D15 to D8 or D7 to D0 at the first RD signal, and the
process is finished ( RD signal going high) before the
higher bits after the second RD signal. If the
new data are latched into its output register, the
ADS8365 is used in the cycle or the FIFO mode, then
possibility still exists that the new data was latched to
the address and data valid information is added to the
the output register just before the falling edge of RD.
data (if ADD is high). In this case, the address will be
If a read process is initiated around 16.5 clock cycles
read first, then the lower eight bits, and finally the
after the conversion started, RD and CS should stay
higher eight bits. If BYTE is low, then the ADS8365
low for at least 50ns (see Figure 1 , t
W6
) to get the
operates in the 16-bit output mode. Here, data are
new data stored to its register and switched to the
read between pins DB15 and DB0. As long as ADD is
output.
low, with every RD impulse, data from a new channel
are brought to the output. If ADD is high and the
cycle or the FIFO mode is chosen; the first output
word contains the address, while the second output
word contains the 16-bit data.
Figure 29. Reading Data in Cycling Mode
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