Datasheet

THEORY OF OPERATION
EXPLANATION OF CLOCK, RESET, FD, AND
t
C1
t
W1
tW3
tW2
tD2
tW4
tD1
CLK
HOLDA
RESET
HOLDB
HOLDC
ADS8365
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.................................................................................................................................................... SBAS362C AUGUST 2006 REVISED MARCH 2008
and all the output registers, aborts any
The ADS8365 contains six 16-bit ADCs that can
conversion in process, and closes the
operate simultaneously in pairs. The three hold
sampling switches. The reset signal must stay
signals ( HOLDA, HOLDB, and HOLDC) initiate the
low for at least 20ns (see Figure 27 , t
W4
). The
conversion on the specific channels. A simultaneous
reset signal should be back high for at least
hold on all six channels can occur with all three hold
20ns (Figure 27 , t
D2
) before starting the next
signals strobed together. The converted values are
conversion (negative hold edge).
saved in six registers. For each read operation, the
ADS8365 outputs 16 bits of information (16 data or 3 EOC End of conversion goes low when new data
channel address, data valid, and some from the internal ADC are latched into the
synchronization information). The address/mode output registers, which usually happens 16.5
signals (A0, A1, and A2) select how the data are read clock cycles after hold initiated the conversion.
from the ADS8365. These address/mode signals can It remains low for half a clock cycle. If more
define a selection of a single channel, a cycle mode than one channel pair is converted
that cycles through all channels, or a FIFO mode that simultaneously, the A-channels get stored to
sequences the data determined by the order of the the registers first (16.5 clock cycles after hold),
hold signals. The FIFO mode will allow the six followed by the B-channels one clock cycle
registers to be used by a single-channel pair; later, and finally the C-channels another clock
therefore, three locations for CH X0 and three cycle later. If a reading (both RD and CS are
locations for CH X1 can be updated before they are low) is in process, then the latch process is
read from the device. delayed until the read operation is finished.
FD First data or A0 data are high if channel A0 is
chosen to be read next. In FIFO mode, the
EOC PINS
channel (X0) that is written to the FIFO first is
latched into the A0 register. For example,
Clock An external clock has to be provided for the
when the FIFO is empty, FD is 0. The first
ADS8365. The maximum clock frequency is
result latched into the FIFO register A0 is,
5MHz. The minimum clock cycle is 200ns (see
therefore, chosen to be read next, and FD
Figure 1 , t
C1
), and the clock has to remain high
rises. After the first channel is read (one to
(Figure 1 , t
W1
) or low for at least 60ns.
three read cycles, depending on BYTE and
RESET Bringing the RESET signal low will reset the
ADD), FD goes low again.
ADS8365. Resetting clears the control register
Figure 27. Start of the Conversion
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