Datasheet

BIPOLAR INPUTS
TRANSITION NOISE
R
1
R
2
+IN
-IN
REF (pin61)
OUT
2.5V
4kW
20kW
Bipolar
Input
BIPOLARINPUT R
1 R2
±10V 1kW 5kW
±5V 2kW 10kW
±2.5V 4kW 20kW
OPA227
ADS8365
OPA227
1.2kW
1.2kW
TIMING AND CONTROL
0
5 00
1000
1500
2000
2500
3000
3500
4000
32782 32783 32784 32785 32786 32787
Code
Occurrences
42
649
3379
603
37
3290
ADS8365
SBAS362C AUGUST 2006 REVISED MARCH 2008 ....................................................................................................................................................
www.ti.com
voltage. Essentially, the current into the ADS8365
charges the internal capacitor array during the
The differential inputs of the ADS8365 were designed
sampling period. After this capacitance has been fully
to accept bipolar inputs ( V
REF
and +V
REF
) around the
charged, there is no further input current. The source
common-mode voltage (2.5V), which corresponds to
of the analog input voltage must be able to charge
a 0V to 5V input range with a 2.5V reference. By
the input capacitance (25pF) to a 16-bit settling level
using a simple op amp circuit featuring four,
within three clock cycles if the minimum acquisition
high-precision external resistors, the ADS8365 can
time is used. When the converter goes into the hold
be configured to accept a bipolar input range. The
mode, the input impedance is greater than 1G .
conventional ± 2.5V, ± 5V, and ± 10V input ranges
Care must be taken regarding the absolute analog
could be interfaced to the ADS8365 using the resistor
input voltage. The +IN and IN inputs should always
values shown in Figure 26 .
remain within the range of AGND 0.3V to AV
DD
+
0.3V.
The OPA365 is a good choice for driving the analog
inputs in a 5V, single-supply application.
The transition noise of the ADS8365 itself is low, as
shown in Figure 25 These histograms were
generated by applying a low-noise dc input and
initiating 8000 conversions. The digital output of the
ADC will vary in output code due to the internal noise
of the ADS8365; this feature is true for all 16-bit,
successive approximation register (SAR) type ADCs.
Using a histogram to plot the output codes, the
distribution should appear bell-shaped, with the peak
of the bell curve representing the nominal code for
the input value. The ± 1 σ , ± 2 σ , and ± 3 σ distributions
Figure 26. Level Shift Circuit for Bipolar Input
represent the 68.3%, 95.5%, and 99.7%, respectively,
Ranges
of all codes. The transition noise can be calculated by
dividing the number of codes measured by 6, yielding
the ± 3 σ distribution, or 99.7%, of all codes.
Statistically, up to three codes could fall outside the
distribution when executing 1000 conversions.
The ADS8365 uses an external clock (CLK, pin 28)
Remember, in order to achieve this low-noise
that controls the conversion rate of the CDAC. With a
performance, the peak-to-peak noise of the input
5MHz external clock, the ADC sampling rate is
signal and reference must be < 50 µ V.
250kSPS which corresponds to a 4 µ s maximum
throughput time. Acquisition and conversion take a
total of 20 clock cycles.
Figure 25. 8000 Conversion Histogram of a DC
Input
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