Datasheet

TIMING CHARACTERISTICS
(1) (2) (3) (4)
ADS8365
SBAS362C AUGUST 2006 REVISED MARCH 2008 ....................................................................................................................................................
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Over recommended operating free-air temperature range, T
MIN
to T
MAX
, AV
DD
= 5V, REF
IN
= REF
OUT
, V
REF
= internal +2.5V,
f
CLK
= 5MHz, f
SAMPLE
= 250kSPS, and BV
DD
= 2.7 to 5V, unless otherwise noted,
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
ACQ
Acquisition time 0.8 µ s
t
CONV
Conversion time 3.2 µ s
t
C1
Cycle time of CLK 200 ns
t
D1
(5)
Delay time of rising edge of CLK after falling edge of HOLDX 10 ns
BV
DD
= 5V 20 ns
t
D2
Delay time of first hold after RESET
BV
DD
= 3V 40 ns
t
D4
Delay time of falling edge of RD after falling edge of CS 0 ns
t
D5
Delay time of rising edge of CS after rising edge of RD 0 ns
BV
DD
= 5V 40 ns
t
D6
Delay time of data valid after falling edge of RD
BV
DD
= 3V 60 ns
BV
DD
= 5V 5 ns
t
D7
Delay time of data hold from rising edge of RD
BV
DD
= 3V 10 ns
BV
DD
= 5V 50 ns
t
D8
Delay time of RD high after CS low
BV
DD
= 3V 60 ns
BV
DD
= 5V 10 ns
t
D9
Delay time of RD low after address setup
BV
DD
= 3V 20 ns
BV
DD
= 5V 10 ns
t
D10
Delay time of data valid to WR low
BV
DD
= 3V 20 ns
BV
DD
= 5V 10 ns
t
D11
Delay time of WR or CS high to data release
BV
DD
= 3V 20 ns
t
W1
Pulse width CLK high time or low time 60 ns
BV
DD
= 5V 15 ns
t
W2
Pulse width of HOLDX high time to be recognized again
BV
DD
= 3V 30 ns
BV
DD
= 5V 20 ns
t
W3
Pulse width of HOLDX low time
BV
DD
= 3V 30 ns
BV
DD
= 5V 20 ns
t
W4
Pulse width of RESET
BV
DD
= 3V 40 ns
BV
DD
= 5V 30 ns
t
W5
Pulse width of RD high time
BV
DD
= 3V 40 ns
BV
DD
= 5V 50 ns
t
W6
Pulse width of RD and CS both low time
BV
DD
= 3V 70 ns
(1) Assured by design.
(2) All input signals are specified with rise time and fall time = 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(3) See Figure 1 .
(4) BYTE is asynchronous; when BYTE is 0, bits 15 to 0 appear at DB15 to DB0. When BYTE is 1, bits 15 to 8 appear on DB7 to DB0. RD
may remain LOW between changes in BYTE.
(5) Only important when synchronization to clock is important.
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