Datasheet
ADS8364
6
SBAS219C
www.ti.com
SPEC DESCRIPTION MIN TYP
(1)
MAX UNITS
t
CONV
Conversion Time 3.2 µs
t
ACQ
Acquistion Time 0.8 µs
t
C1
Cycle Time of CLK 200 ns
t
W1
Pulse Width CLK HIGH Time or LOW Time. 60 ns
t
D1
(5)
Delay Time of Rising Edge of Clock After Falling Edge of HOLD (A,B,C) 10 ns
t
W2
Pulse Width of HOLDX HIGH Time to be Recognized again BV
DD
= 5V 15 ns
BV
DD
= 3V 30 ns
t
W3
Pulse Width of HOLDX LOW Time BV
DD
= 5V 20 ns
BV
DD
= 3V 30 ns
t
W4
Pulse Width of RESET BV
DD
= 5V 20 ns
BV
DD
= 3V 40 ns
t
W5
Pulse Width of RD HIGH Time BV
DD
= 5V 30 ns
BV
DD
= 3V 40 ns
t
D2
Delay Time of First Hold After RESET BV
DD
= 5V 20 ns
BV
DD
= 3V 40 ns
t
D4
Delay Time of Falling Edge of RD After Falling Edge of CS 0 ns
t
D5
Delay Time of Rising Edge of CS After Rising Edge of RD 0 ns
t
W6
Pulse Width of RD and CS Both LOW Time BV
DD
= 5V 50 ns
BV
DD
= 3V 70 ns
t
W7
Pulse Width of RD HIGH Time BV
DD
= 5V 20 ns
BV
DD
= 3V 40 ns
t
D6
Delay Time of Data Valid After Falling Edge RD BV
DD
= 5V 40 ns
BV
DD
= 3V 60 ns
t
D7
Delay Time of Data Hold From Rising Edge of RD BV
DD
= 5V 5 ns
BV
DD
= 3V 10 ns
t
D8
Delay Time of RD HIGH After CS LOW BV
DD
= 5V 50 ns
BV
DD
= 3V 60 ns
t
D9
Delay Time of RD Low After Address Setup BV
DD
= 5V 10 ns
BV
DD
= 3V 20 ns
NOTES: (1) Assured by design. (2) All input signals are specified with tr = tf = 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(3) See timing diagram above. (4) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BYTE is 1, bits 15 through 8
appear on DB7-DB0. RD may remain LOW between changes in BYTE. (5) Only important when synchronization to clock is important.
TIMING CHARACTERISTICS TABLE
Timing Characteristics over recommended operating free-air temperature range T
MIN
to T
MAX
, AV
DD
= DV
DD
= 5V, REF
IN
= REF
OUT
internal reference +2.5V,
f
CLK
= 5MHz, f
SAMPLE
= 250kSPS, BV
DD
= 2.7 ÷ 5V (unless otherwise noted).
TIMING CHARACTERISTICS
t
W6
t
D6
t
D4
t
D5
t
D7
t
W5
t
W1
t
D1
t
C1
t
W3
CONVERSION
t
CONV
ACQUISITION
t
ACQ
t
W2
Bits 15-8
Bits 7-0
Bits 15-8
Bits 7-0
CLK
HOLDX
EOC
CS
RD
D15-D8
D7-D0
BYTE
1 2 16 17 18 19 20 1 2