Datasheet

ADS8364
17
SBAS219C
www.ti.com
FIGURE 12. Functionality Diagram of FIFO Registers.
a2 a1 a0
Data From Channel A0 0 0 0
Data From Channel A1 0 0 1
Data From Channel B0 0 1 0
Data From Channel B1 0 1 1
Data From Channel C0 1 0 0
Data From Channel C1 1 0 1
TABLE VI. Address Bit in the Output Data.
ing power supplies, nearby digital logic, or high-power de-
vices. The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of the
external event. Their error can change if the external event
changes in time with respect to the CLK input.
With this in mind, power to the ADS8364 should be clean and
well-bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1µF
to 10µF capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be used to low-
pass filter a noisy supply. On average, the ADS8364 draws
very little current from an external reference as the reference
voltage is internally buffered. A bypass capacitor of 0.1µF and
10µF are suggested when using the internal reference (tie pin
61 directly to pin 62).
GROUNDING
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the analog ground.
Avoid connections that are too close to the grounding point
of a microcontroller or digital signal processor. If required,
run a ground trace directly from the converter to the power-
supply entry point. The ideal layout will include an analog
ground plane dedicated to the converter and associated
analog circuitry. Three signal ground pins, SGND, are the
input signal grounds which are on the same potential as
analog ground.
APPLICATION INFORMATION
In Figures 13 through 18, different connection diagrams to
DSPs or micro-controllers are shown.
(db7…db0) and finally the higher eight data bits (db15…db8).
1000 0000 0000 is added before the address in case BYTE =
0 and db3…db0 after the address if BYTE = 1. This provides
the possibility to check if the counting of the
RD signals
inside the ADS8364 are still tracking with the external inter-
face (see Table III and Table IV).
The data valid bit is useful for the FIFO mode. Valid data can
simply get read until dv turns 0. The three address bits are
listed in Table VI. If the FIFO is empty, 16 zeroes are put to
the output.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8364 circuitry. This is particularly
true if the CLK input is approaching the maximum throughput
rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, driving any single
conversion for an n-bit SAR converter, there are n
windows
in which large external transient voltages can affect the
conversion result. Such glitches might originate from switch-
RESET
EOC
RD
reg. 5
reg. 4
reg. 3
reg. 2
reg. 1
reg. 0
empty
empty
empty
empty
empty
empty
empty
empty
empty
empty
ch A1
ch A0
empty
empty
empty
empty
empty
ch A1
empty
ch C1
ch C0
ch B1
ch B0
ch A1
empty
empty
ch C1
ch C0
ch B1
ch B0
ch C1
ch C0
ch C1
ch C0
ch B1
ch B0
Conversion
Channel A
Conversion
Channel C
Conversion
Channels B and C
t
0
t
1
t
2
t
3
t
4
t
5