Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 64

250kSPS, 16-Bit, 6-Channel

Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTERS

FEATURES

● 6 INPUT CHANNELS

● FULLY DIFFERENTIAL INPUTS

● 6 INDEPENDENT 16-BIT ADC

● 4µs TOTAL THROUGHPUT PER CHANNEL

●

TESTED NO MISSING CODES TO 14 BITS

● BUFFERED REFERENCE INPUTS

● LOW POWER: 450mW

● TQFP-64 PACKAGE

APPLICATIONS

● MOTOR CONTROL

● MULTI-AXIS POSITIONING SYSTEMS

● 3-PHASE POWER CONTROL

DESCRIPTION

The ADS8364 includes six, 16-bit, 250kSPS ADCs (Analog-

to- Digital converters) with 6 fully differential input channels

grouped into two pairs for high-speed simultaneous signal

acquisition. Inputs to the sample-and-hold amplifiers are fully

differential and are maintained differential to the input of the

ADC. This provides excellent common-mode rejection of

80dB at 50KHz that is important in high-noise environments.

The ADS8364 offers a flexible high-speed parallel interface

with a direct address mode, a cycle, and a FIFO mode. The

output data for each channel is available as a 16-bit word.

ADS8364

SBAS219C – JUNE 2002 – REVISED AUGUST 2006

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

836

Interface

Conversion

and

Control

FIFO

EOC

Data

Input/Output

RESET

BYTE

CLK

CH A0–

CH A0+

CH A1–

CH A1+

SAR

CDAC

S/H

Amp

Comp

CDAC

Comp

S/H

Amp

CH B0–

CH B0+

HOLDA

CH B1–

CH B1+

SAR

CDAC

S/H

Amp

Comp

CDAC

Comp

S/H

Amp

CH C0–

CH C0+

CH C1–

CH C1+

REF

OUT

SAR

CDAC

S/H

Amp

Comp

CDAC

Comp

S/H

Amp

HOLDB

HOLDC

ADD

Internal

2.5V

Reference

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

All trademarks are the property of their respective owners.

Summary of content (26 pages)

PAGE 1
ADS8364 ADS 836 ® 4 SBAS219C – JUNE 2002 – REVISED AUGUST 2006 250kSPS, 16-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS FEATURES DESCRIPTION ● ● ● ● ● ● ● ● The ADS8364 includes six, 16-bit, 250kSPS ADCs (Analogto- Digital converters) with 6 fully differential input channels grouped into two pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC.
PAGE 2
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)(1) Supply Voltage, AGND to AVDD ............................................................... –0.3V to 6V Supply Voltage, BGND to BVDD ............................................................... –0.3V to 6V Supply Voltage, DGND to DVDD .............................................................. –0.3V to 6V Analog Input Voltage Range ...................
PAGE 3
ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = DVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted. ADS8364Y PARAMETER CONDITIONS ANALOG INPUT Full-Scale Range Operating Common-Mode Signal Input Resistance Input Capacitance Input Leakage Current Differential Input Resistance Differential Input Capacitance Common-Mode Rejection Ratio (FSR) TYP(1) MAX UNITS ±VREF 2.
PAGE 4
ELECTRICAL CHARACTERISTICS (Cont.) Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = DVDD = 5V, VREF = internal +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted. ADS8364Y PARAMETER CONDITIONS MIN TYP(1) MAX UNITS BVDD + 0.3 0.
PAGE 5
A2 ADD RESET 57 56 55 54 53 52 51 50 BGND A1 58 BVDD A0 AVDD 59 HOLD A 60 HOLD B 61 HOLD C 62 AGND 63 REFOUT CH A0+ 64 REFIN CH A0– PIN CONFIGURATION 49 CH A1– 1 48 D0 CH A1+ 2 47 D1 AVDD 3 46 D2 AGND 4 45 D3 SGND 5 44 D4 CH B0+ 6 43 D5 CH B0– 7 42 D6 AVDD 8 AGND 9 41 D7 ADS8364 40 D8 SGND 10 39 D9 CH B1– 11 38 D10 CH B1+ 12 37 D11 27 28 29 30 31 32 BGND BGND 26 CS 25 WR 24 RD 23 CLK 22 EOC 21 FD 20 BVDD 19 BYTE 18 DV
PAGE 6
TIMING CHARACTERISTICS tC1 CLK 1 tW1 2 16 17 18 tD1 19 20 1 2 ACQUISITION tACQ CONVERSION tCONV HOLDX tW3 tW2 EOC CS tD4 tD5 tW6 RD tW5 tD6 tD7 D15-D8 Bits 15-8 Bits 15-8 D7-D0 Bits 7-0 Bits 7-0 BYTE TIMING CHARACTERISTICS TABLE Timing Characteristics over recommended operating free-air temperature range TMIN to TMAX, AVDD = DVDD = 5V, REFIN = REFOUT internal reference +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS, BVDD = 2.7 ÷ 5V (unless otherwise noted).
PAGE 7
TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted. INTEGRAL LINEARITY ERROR vs CODE 5 4 Typical curve for all six channels.
PAGE 8
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted. SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 100 1.0 0.8 90 SNR and SINAD (dB) 95 SNR and SINAD (dB) DELTA OF SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE (ALL CH) SNR 85 80 SINAD 75 0.6 SNR 0.4 0.2 0.0 –0.2 –0.4 SINAD –0.6 70 –0.8 65 –1.
PAGE 9
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted. POSITIVE GAIN MATCH OF ALL CHANNELS vs TEMPERATURE 0.0025 Channel B 0.0020 Channel A 0.0015 Channel C 0.0010 –50 –25 0 25 50 75 NEGATIVE GAIN MATCH OF ALL CHANNELS vs TEMPERATURE 0.0025 Negative Gain Match (%FSR) Positive Gain Match (%FSR) 0.0030 Channel C 0.0020 Channel A 0.0015 Channel B 0.0010 0.0005 0.
PAGE 10
INTRODUCTION The ADS8364 is a high-speed, low-power, 6-channel simultaneous sampling and converting, 16-bit ADC that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains six 4µs successive approximation ADCs, six differential sample-and-hold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins and a high-speed parallel interface.
PAGE 11
+IN CM + VREF +VREF CM Voltage –IN = CM Voltage –VREF t CM – VREF Single-Ended Inputs +IN CM + 1/2VREF +VREF CM Voltage –VREF –IN CM – 1/2VREF t Differential Inputs NOTES: Common-Mode Voltage (Differential Mode) = (+IN) + (–IN) , Common-Mode Voltage (Single-Ended Mode) = IN–. 2 The maximum differential voltage between +IN and –IN of the ADS8364 is VREF. See Figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs. FIGURE 2.
PAGE 12
current into the ADS8364 charges the internal capacitor array during the sampling period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to a 16-bit settling level within 3 clock cycles if the minimum acquisition time is used. When the converter goes into the hold mode, the input impedance is greater than 1GΩ. R1 4kΩ 1.
PAGE 13
EOC—End of conversion goes low when new data of the internal ADC is latched into the output registers, which usually happens 16.5 clock cycles after hold initiated the conversion. It remains low for half a clock cycle. If more than one channel pair is converted simultaneously, the A-channels get stored to the registers first (16.5 clock cycles after hold), followed by the B-channels one clock cycle later, and finally the C-channels at another clock cycle later.
PAGE 14
CONVERSION CLK 1 2 ACQUISITION 16 17 18 19 20 1 2 HOLD B EOC CS RD A0 FIGURE 8. Timing of one Conversion Cycle. CLK 16 17 18 19 20 1 2 tD1 HOLD X tACQ EOC CS tD8 tW7 RD tD9 A0 FIGURE 9. Timing for Reading Data. register, the possibility still exists that the new data was latched to the output register just before the falling edge of RD. If a read process is initiated around 16.
PAGE 15
0111111111111111 65535 0111111111111110 65534 0111111111111101 65533 0000000000000001 32769 0000000000000000 32768 1111111111111111 32767 1000000000000010 Step Digital Output Code Binary Two's Complement BTC 2 1000000000000001 1 1000000000000000 0 2.499962V VNFS = VCM – VREF = 0V 0.000038V 2.500038V VPFS = VCM + VREF = 5V VPFS – 1LSB = 4.999924V VBPZ = 2.5V 0.000076V 4.999848V Unipolar Analog Input Voltage 1LSB = 76µV 0.000152V VCM = 2.5V 16-BIT VREF = 2.
PAGE 16
ADD = 0 BYTE = 0 BYTE = 1 A2 A1 A0 1st RD 2nd RD 1st RD 2nd RD 3rd RD 000 001 010 011 100 101 110 111 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db15...
PAGE 17
RESET EOC Conversion Channel A Conversion Channels B and C Conversion Channel C RD reg. 5 empty empty empty empty empty ch C1 reg. 4 empty empty empty ch C1 empty ch C0 reg. 3 empty empty empty ch C0 ch C1 ch C1 reg. 2 empty empty empty ch B1 ch C0 ch C0 reg. 1 empty ch A1 empty ch B0 ch B1 ch B1 reg. 0 empty ch A0 ch A1 ch A1 ch B0 ch B0 t1 t0 t2 t3 t4 t5 FIGURE 12. Functionality Diagram of FIFO Registers.
PAGE 18
3.3V ADS8364 DVDD BVDD BVDD HOLDA HOLDB 26 30 23 55 HOLDC FD WR A0 ADD A1 BYTE A2 CS 56 PWM1 57 PWM2 58 PWM3 54 EA0 53 EA1 52 EA2 EA3 31 8:1 OE RD EOC CLK RESET C28xx IS 29 RE 27 EXT_INT1 28 MCLKX 51 ADC_RST (MFSX) DATA [0] ... DATA [15] D0 ... D15 48 ... 33 VSS BGND FIGURE 13. Typical C28xx Connection (Hardware Control). BVDD 3.
PAGE 19
3.3V ADS8364 DVDD BVDD BVDD HOLDA HOLDB 26 54 53 52 30 23 55 FD HOLDC 56 TOUT0 57 A2 58 A1 8:1 A0 CS A1 C54xx 31 A0 OE IS 29 A2 RD WR 30 27 ADD EOC BYTE CLK <1 I/OSTRB (1G32) 28 INT0 51 BCLKX1 RESET XF DATA [0] ... DATA [15] D0 ... D15 48 ... 33 VSS BGND FIGURE 15. Typical C54xx Connection (FIFO with Hardware Control). 3.
PAGE 20
BVDD 3.3V ADS8364 56 57 58 26 23 55 54 HOLDA C67xx DVDD BVDD HOLDB HOLDC A2 A1 FD 8:1 ADD BYTE CS A0 RD 31 A0 IS OE 29 RE 30 53 A1 WR 52 A2 EOC CLK WE 27 INT0 28 TOUT0 DATA [0] ... DATA [15] D0 ... D15 48 ... 33 VSS BGND FIGURE 17. Typical C67xx Connection (Software Control). 3.3V ADS8364 BVDD DVDD BVDD HOLDA 30 52 54 53 23 55 29 WR HOLDB ADD HOLDC A1 A2 CS RESET BYTE EOC A0 CLK RD DATA [0] ... DATA [7] MSP430x1xx 56 TACLK (P1.0) 57 58 31 P1.1 51 P1.
PAGE 21
Revision History DATE REVISION PAGE 8/06 SECTION 1 — 2 Dissipation Ratings Table DESCRIPTION Changed Throughput Rate from 250kHz to 250kSPS throughout document. C Changed package from DGK to PAG. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ADS8364 SBAS219C www.ti.
PAGE 22
PACKAGE OPTION ADDENDUM www.ti.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8364Y/250 TQFP PAG 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS8364Y/2K TQFP PAG 64 2000 330.0 24.4 13.0 13.0 1.5 16.0 24.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8364Y/250 TQFP PAG ADS8364Y/2K TQFP PAG 64 250 367.0 367.0 45.0 64 2000 367.0 367.0 45.
PAGE 25
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 26
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.