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3.1 Additional Control Options

Table 3 shows the pinout of J2. This dual row, four-position header provides additional control functionality

to the ADS7263/8363EVM. Signals A0, M0, and M1 are configured with pull-up resistors by default. The

jumper shunts supplied with the EVM can be used to set these signals to logic low. These signals can also

be connected to control signals in your system.

Table 3. J2 Control Header Pinout

Pin Number Signal Description

J2.1 M1 Selects two-channel or four-channel mode

J2.3 M0 Selects between serial outputs A and B

J2.5 SDOB B channel secondary output

4 Power Supplies

The ADS7263/8363EVM board requires +5 V

for the analog section and either +5V or +3.3V

for the

digital section. While filters are provided for all power-supply inputs, optimal performance of the EVM

requires a clean, well-regulated power source. +5-V

power is applied to J4 pin 3 referenced to pin 5.

The digital supply of +3.3V or +5V is applied to J4 pin 9 or J4 pin 10 (respectively), referenced to J4 pin 6.

NOTE: The shunt jumper at location JP6 is placed across pins 1-2. This configuration is the factory

default for both the ADS7263EVM and ADS8363EVM.

4.1 Reference Voltage

The ADS7263/8363 can be configured to use its internal reference, or external reference source through

jumper JP3 and JP4 (see schematic for details). If an external reference is desired, a clean voltage source

may be applied to TP4 or TP5 referenced to analog ground at TP3.

5 EVM Operation

This section provides information on the analog input, digital control, and general operating conditions of

the ADS7263/8363EVM.

The analog input source can be applied directly to J1 (top or bottom side) or through optional amplifier and

signal conditioning modules. The analog input level should not exceed 5.0 V

. The analog input range is

from –VREF to +VREF (0 to 5 V

) centered at 2.5 V.

The digital control signals can be applied directly to J3 (top or bottom side). The ADS7263/8363EVM can

also be connected directly to a DSP interface board. Refer to the ADS7263 and ADS8363 device product

folders for a complete list of DSP interface cards and optional analog interface modules.

Jumper JP5 is provided to allow the separation of the convert start (CONVST) and read (RD) signals. The

factory default condition for the EVM is to have a shunt jumper placed between pins 1-2 of JP5. This

configuration combines the RD and CONVST signals, which are applied to the ADC via J3.7. When JP5 is

moved to pins 2-3, the RD signal is applied via J2.7 while CONVST is applied to J3.17.

J2 is provided as a means to access the M0 and M1 control lines as well as the OUTB serial data. Shunt

jumpers are placed on J2 pins 3-4, which defaults M0 to a logic low state. Removing the jumpers allows

these lines to go to logic high levels through the associated pull-up resistors R12 and R13.

6 Schematics and Layout

Schematics for the ADS7263/8363EVM are appended to this user's guide. The bill of materials is provided

in Table 4.

ADS7263/8363 SBAU185–January 2011

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