Datasheet

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Analog Interface

2 Analog Interface

For maximum flexibility, the ADS7263/8363EVM is designed for easy interfacing to multiple analog

sources. Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient,

10-pin dual row header/socket combination at J1. This header/socket provides access to the analog input

pins of the ADC. Consult Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of

mating connector options. Use appropriate caution when handling these pins. Table 1 summarizes the

pinouts for the analog interface J1.

Table 1. J1: Analog Interface Pinout

Pin Number Signal Description

J1.2 B1+ Noninverting input, Channel B1

J1.4 B1– Inverting input, Channel B1

J1.6 B0+ Noninverting input, Channel B0

J1.8 B0– Inverting input, Channel B0

J1.10 A1+ Noninverting input, Channel A1

J1.12 A1– Inverting input, Channel A1

J1.14 A0+ Noninverting input, Channel A0

J1.16 A0– Inverting input, Channel A0

J1.18 Unused Pins are unused and should be left open for use with future

amplifier and sensor input modules.

J1.20 REFIN External reference source input (2.5 V nom, 2.525 V max)

J1.1 to J1.19 (odd) AGND Analog ground connections

3 Digital Interface

The ADS7263/8363EVM is designed for easy interfacing to multiple control platforms. Samtec part

numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient, 10-pin dual row

header/socket combination at J3. This header/socket provides access to the digital control and serial data

pins of the THS1218. Consult Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of

mating connector options. Table 2 describes the J2 serial interface pins.

Table 2. J3: Serial Interface Pinout

Pin Number Signal Description

J3.1 CS Chip select; active low signal. Enables data transfer and

device configuration.

J3.3 SCLK Serial clock

J3.5 SCLK(R) Serial clock return for DSP host

J3.7 FS RD input

J3.9 FS(R) Frame sync return for DSP host

J3.11 SDI Serial data input

J3.13 SDO Serial data output

J3.15 INT Busy output; provides an interrupt source to host processor

J3.17 CSTART Conversion start; provides alternate method of conversion

initialization

J3.19 SPARE —

SBAU185–January 2011 ADS7263/8363

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