Datasheet

ADS8361
7
SBAS230E
www.ti.com
SYMBOL DESCRIPTION MIN MAX UNITS COMMENTS
t
CONV
Conversion Time 1.6 μs When T
CKP
= 100ns
t
ACQ
Acquisition Time 0.4 μs When T
CKP
= 100ns
t
CKP
Clock Period 100 10,000 ns
t
CKL
Clock LOW 40 ns
t
CKH
Clock HIGH 40 ns
t
F
DOUT Fall Time 25 ns
t
R
DOUT Rise Time 30 ns
t
1
CONVST HIGH 15 ns
t
2
Address Setup Time 15 ns Address latched on falling edge of CLK cycle ‘2’.
t
3
Address Hold Time 15
t
4
RD Setup Time 15 ns Before falling edge of CLOCK.
t
5
RD to CS Hold Time 15 ns After falling edge of CLOCK.
t
6
CONVST LOW 20 ns
t
7
RD LOW 20 ns
t
8
CS Setup Time 15 ns Before falling edge of CLOCK (for RD).
t
9
CLOCK to Data Valid Delay 30 ns Maximum delay following rising edge of CLOCK.
t
10
Data Valid After CLOCK
(3)
1 ns Time data is valid after second rising edge of CLOCK.
t
11
CS Setup Time 0 ns Before CONVST
TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
Timing Characteristics over recommended operating free-air temperature range T
MIN
to T
MAX
, AV
DD
= 5V, REF
IN
= REF
OUT
internal reference +2.5V,
f
CLK
= 10MHz, f
SAMPLE
= 500kSPS, and BV
DD
= 2.7 ÷ 5.5V (unless otherwise noted).
NOTES: (1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See timing diagram above.
(3) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle.
CH
A/B
CH
0/1
A0
RD
CS
BUSY
Serial
Data A
1CLOCK
CONVST
234 1110 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6
D15 D14
D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12
Serial
Data B
D15 D14 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12
CH
0/1
0
t
3
t
1
t
CONV
t
ACQ
t
CONV
t
7
t
10
t
9
t
6
t
CKH
t
CKL
0
t
2
t
11
t
4
t
8
t
8
t
5