Datasheet

ADS8361
12
SBAS230E
www.ti.com
FIGURE 5. Histogram of 8000 Conversions of a DC Input.
FIGURE 6. Test Circuits for Timing Specifications.
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
TRANSITION NOISE
The transition noise of the ADS8361 itself is low,
as shown in Figure 5. These histograms were generated by
applying a low-noise DC input and initiating 8000 conversions.
The digital output of the A/D converter will vary in output code
due to the internal noise of the ADS8361. This is true for all 16-
bit, Successive Approximation Register (SAR-type) A/D con-
verters. Using a histogram to plot the output codes, the
distribution should appear bell-shaped with the peak of the bell
curve representing the nominal code for the input value. The
±1σ, ±2σ, and ±3σ distributions will represent the 68.3%,
95.5%, and 99.7%, respectively, of all codes. The transition
noise can be calculated by dividing the number of codes
measured by 6 and this will yield the ±3σ distribution, or
99.7%, of all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000 conversions.
Remember, to achieve this low-noise performance, the peak-
to-peak noise of the input signal and reference must be
< 50μV.
R
1
R
2
+IN
–IN
REF
OUT
(pin 11)
2.5V
4kΩ
20kΩ
Bipolar Input
BIPOLAR INPUT R
1
R
2
±10V 1kΩ 5kΩ
±5V 2kΩ 10kΩ
±2.5V 4kΩ 20kΩ
OPA227
ADS8361
OPA227
600Ω
600Ω
DATA
1.4V
Test Point
3kΩ
100pF
C
LOAD
t
R
DATA
Voltage Waveforms for DATA Rise-and-Fall Times t
R
, and t
F
.
V
OH
V
OL
t
F
BIPOLAR INPUTS
The differential inputs of the ADS8361 were designed to
accept bipolar inputs (–V
REF
and +V
REF
) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resistors,
the ADS8361 can be configured to except bipolar inputs. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
interfaced to the ADS8361 using the resistor values shown in
Figure 7.
Code (decimal)
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
Number of Conversions
32761 32762 3276432763 32765 32766
TIMING AND CONTROL
The operation of the ADS8361 can be configured in four
different modes by using the address pins M0 (pin 14), M1
(pin 15), and A0 (pin 16).
The M0 pin selects between two- and four-channel operation
(in two-channel operation, the A0 pin selects between Chan-
nels 0 and 1; in four-channel operation the A0 pin is ignored
and the channels are switched automatically after each
conversion). The M1 pin selects between having serial data
transmitted simultaneously on both the Serial A data output
(pin 23) and the Serial B data output (pin 22) or having both
channels output data through the Serial A port. The A0 pin
selects either Channel 0 or Channel 1 (see Pin Descriptions
and Serial Output Truth Table for more information).
The next four sections will explain the four different modes of
operation.
Mode I (M0 = 0, M1 = 0)
With the M0 and M1 pins both set to ‘0’, the ADS8361 will
operate in two-channel operation (the A0 pin must be used
to switch between Channels A and B). A conversion is
initiated by bringing CONVST HIGH for a minimum of 15ns.
It is very important that CONVST be brought HIGH a mini-
mum of 10ns prior to a falling edge of the external clock or
5ns after the falling edge. If CONVST is brought HIGH within
this window, it is then uncertain as to when the ADS8361 will
initiate conversion (see Figure 9 for a more detailed descrip-