Datasheet

ADS8344
16
SBAS139E
FIGURE 9. Histogram of 5,000 Conversions of a DC Input at the
Code Center, 5V operation internal clock mode.
Code
4507
25100242
7FFE7FFD 800180007FFF
FIGURE 10. Histogram of 5,000 Conversions of a DC Input at the
Code Transition, 2.7V operation external clock mode.
FIGURE 11. Histogram of 5,000 Conversions of a DC Input at the
Code Center, 2.7V operation internal clock mode.
Code
3511
721666
50 52
7FFE7FFD 800180007FFF
Code
2868
1137
858
78 59
7FFE7FFD 800180007FFF
sion results will reduce the transition noise by 1/2 to
±0.25LSBs. Averaging should only be used for input signals
with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging: for every decimation by 2, the
signal-to-noise ratio will improve 3dB.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8344 circuitry. This is particu-
larly true if the reference voltage is LOW and/or the conver-
sion rate is HIGH.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high-power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
With this in mind, power to the ADS8344 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS8344 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS8344 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While
high-frequency noise can be filtered out as discussed in the
previous paragraph, voltage variation due to line frequency
(50Hz or 60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections that are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power-supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conver-