Datasheet
ADS8344
14
SBAS139E
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 1.5 µs
t
DS
D
IN
Valid Prior to DCLK Rising 100 ns
t
DH
D
IN
Hold After DCLK HIGH 10 ns
t
DO
DCLK Falling to D
OUT
Valid 200 ns
t
DV
CS Falling to D
OUT
Enabled 200 ns
t
TR
CS Rising to D
OUT
Disabled 200 ns
t
CSS
CS Falling to First DCLK Rising 100 ns
t
CSH
CS Rising to DCLK Ignored 0 ns
t
CH
DCLK HIGH 200 ns
t
CL
DCLK LOW 200 ns
t
BD
DCLK Falling to BUSY Rising 200 ns
t
BDV
CS Falling to BUSY Enabled 200 ns
t
BTR
CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V to 3.6V,
T
A
= –40°C to +85°C, C
LOAD
= 50pF).
Since one clock cycle of the serial clock is consumed with
BUSY going HIGH (while the MSB decision is being
made), 16 additional clocks must be given to clock out all 16
bits of data; thus, one conversion takes a minimum of 25
clock cycles to fully read the data. Since most microproces-
sors communicate in 8-bit transfers, this means that an
additional transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
where the beginning of the next control byte appears at the
same time the LSB is being clocked out of the ADS8344
(see Figure 3). This method allows for maximum throughput
and 24 clock cycles per conversion.
The other method is shown in Figure 5, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the D
OUT
line. BUSY and D
OUT
go into a
high-impedance state when CS goes HIGH; after the next
CS falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8344 generates its own
conversion clock internally. This relieves the microproces-
sor from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate from 0MHz to 2.0MHz.
BUSY goes LOW at the start of a conversion and then
returns HIGH when the conversion is complete. During the
conversion, BUSY will remain LOW for a maximum of 8µs.
Also, during the conversion, DCLK should remain LOW to
achieve the best noise performance. The conversion result is
stored in an internal register; the data may be clocked out of
this register any time after the conversion is complete.
t
ACQ
AcquireIdle Conversion
1D
CLK
CS
81
15
D
OUT
BUSY
(MSB)
(START)
(LSB)
A2S
D
IN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0
81 8
Idle
18
Zero Filled...
If CS is LOW when BUSY goes LOW following a conver-
sion, the next falling edge of the external serial clock will
write out the MSB on the D
OUT
line. The remaining bits
(D14-D0) will be clocked out on each successive clock cycle
following the MSB. If CS is HIGH when BUSY goes LOW
then the D
OUT
line will remain in tri-state until CS goes
LOW, as shown in Figure 6. CS does not need to remain
LOW once a conversion has started. Note that BUSY is not
tri-stated when CS goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8344 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time t
ACQ
, is kept above 1.7µs.
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for
the digital interface of the ADS8344.
t
ACQ
AcquireIdle Conversion
1D
CLK
CS
8
9 1011121314151617181920212223242526272829303132
15
D
OUT
BUSY
(MSB)
(START)
(LSB)
A2S
D
IN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
FIGURE 5. External Clock Mode, 32 Clocks Per Conversion.
FIGURE 6. Internal Clock Mode Timing.