Datasheet

ADS8344
13
SBAS139E
The first eight clock cycles are used to provide the control
byte via the D
IN
pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After four more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample-and-hold goes into the Hold
mode. The next sixteen clock cycles accomplish the actual
A/D conversion.
Control Byte
See Figure 3 for placement and order of the control bits
within the control byte. Tables III and IV give detailed
information about these bits. The first bit, the “S” bit, must
always be HIGH and indicates the start of the control byte.
The ADS8344 will ignore inputs on the D
IN
pin until the
START bit is detected. The next three bits (A2-A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
BIT 7 BIT 0
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB)
SA2A1A0— SGL/DIF PD1 PD0
TABLE III. Order of the Control Bits in the Control Byte.
TABLE IV.Descriptions of the Control Bits within the
Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first HIGH bit on
D
IN
.
6 - 4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input,
see Tables I and II.
2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input, see Tables I and II.
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
details.
PD1 PD0 DESCRIPTION
0 0 Power-down between conversions. When each
conversion is finished, the converter enters a
low-power mode. At the start of the next conver-
sion, the device instantly powers up to full power.
There is no need for additional delays to assure full
operation and the very first conversion is valid.
1 0 Selects Internal Clock Mode.
0 1 Reserved for Future Use.
1 1 No power-down between conversions, device al-
ways powered. Selects external clock mode.
TABLE V. Power-Down Selection.
FIGURE 4. Detailed Timing Diagram.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
15 D
OUT
BUSY
D
IN
14
HIGH, the device is always powered up. If both PD1 and
PD0 are LOW, the device enters a power-down mode
between conversions. When a new conversion is initiated,
the device will resume normal operation instantly—no delay
is needed to allow the device to power up and the very first
conversion will be valid.
Clock Modes
The ADS8344 can be used with an external serial clock or an
internal clock to perform the successive-approximation con-
version. In both clock modes, the external clock shifts data in
and out of the device. Internal clock mode is selected when
PD1 is HIGH and PD0 is LOW.
If the user decides to switch from one clock mode to the other,
an extra conversion cycle will be required before the
ADS8344 can switch to the new mode. The extra cycle is
required because the PD0 and PD1 control bits need to be
written to the ADS8344 prior to the change in clock modes.
When power is first applied to the ADS8344, the user must
set the desired clock mode. It can be set by writing PD1
= 1 and PD0 = 0 for internal clock mode or PD1 = 1 and PD0
= 1 for external clock mode. After enabling the required
clock mode, only then should the ADS8344 be set to power-
down between conversions (i.e., PD1 = PD0 = 0). The
ADS8344 maintains the clock mode it was in prior to
entering the power-down modes.
External Clock Mode
In external clock mode, the external clock not only shifts data
in and out of the ADS8344, it also controls the A/D conversion
steps. BUSY will go HIGH for one clock period after the last
bit of the control byte is shifted in. Successive-approximation
bit decisions are made and appear at D
OUT
on each of the next
16 DCLK falling edges (see Figure 3). Figure 4 shows the
BUSY timing in external clock mode.
The SGL/DIF-bit controls the multiplexer input mode: ei-
ther in single-ended mode, where the selected input channel
is referenced to the COM pin, or in differential mode, where
the two selected inputs provide a differential input.
See Tables I and II and Figure 2 for more information. The
last two bits (PD1 - PD0) select the power-down mode and
Clock mode, as shown in Table V. If both PD1 and PD0 are