Datasheet

ADS8343
16
SBAS183C
www.ti.com
NOISE
The noise floor of the ADS8343 itself is extremely low, as can
be seen from Figures 12 and 13, and is much lower than
competing A/D converters. The ADS8343 was tested at both
5V and 2.7V and in both the internal and external clock
modes. A low-level DC input was applied to the analog input
pins and the converter was put through 5000 conversions.
The digital output of the A/D converter will vary in output code
due to the internal noise of the ADS8343. This is true for all
16-bit, SAR-type, A/D converters. Using a histogram to plot
the output codes, the distribution should appear bell-shaped
with the peak of the bell curve representing the nominal code
for the input value. The ±1σ, ±2σ, and ±3σ distributions will
represent the 68.3%, 95.5%, and 99.7%, respectively, of all
codes. The transition noise can be calculated by dividing the
number of codes measured by 6 and this will yield the ±3σ
distribution or 99.7% of all codes. Statistically, up to 3 codes
could fall outside the distribution when executing 1000 con-
versions. The ADS8343, with < 3 output codes for the ±3σ
distribution, will yield a < ±0.5LSB transition noise at 5V
operation. Remember, to achieve this low noise perfor-
mance, the peak-to-peak noise of the input signal and
reference must be < 50µV.
FIGURE 12. Histogram of 5000 Conversions of a DC Input at the
Code Transition, 5V Operation External Clock Mode.
FIGURE 13. Histogram of 5000 Conversions of a DC Input at the
Code Center, 2.7V Operation Internal Clock Mode.
3295
774
95
131
705
FFFE
H
FFFF
H
0000
H
0001
H
0002
H
Code
2387
694
905
512
411
38 38
87
FFFE
H
FFFD
H
FFFC
H
FFFF
H
0000
H
0001
H
0002
H
0003
H
0004
H
Code
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/
√n , where n
is the number of averages. For example, averaging 4 conver-
sion results will reduce the transition noise by 1/2 to
±0.25LSBs. Averaging should only be used for input signals
with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signal-
to-noise ratio will improve 3dB.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8343 circuitry. This is particularly true
if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections,
and digital inputs that occur just prior to latching the output of the
analog comparator. Thus, during any single conversion for an n-
bit SAR converter, there are n “windows” in which large external
transient voltages can easily affect the conversion result. Such
glitches might originate from switching power supplies, nearby
digital logic, and high-power devices. The degree of error in the
digital output depends on the reference voltage, layout, and the
exact timing of the external event. The error can change if the
external event changes in time with respect to the DCLK input.
With this in mind, power to the ADS8343 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1µF
to 10µF capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS8343 draws very little
current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS8343 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply will
appear directly in the digital results. While high-frequency
noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In
many cases, this will be the “analog” ground. Avoid connec-
tions which are too near the grounding point of a microcontroller
or digital signal processor. If needed, run a ground trace
directly from the converter to the power-supply entry point. The
ideal layout will include an analog ground plane dedicated to
the converter and associated analog circuitry.