Datasheet

ADS8343
15
SBAS183C
www.ti.com
DATA FORMAT
The output data from the ADS8343 is in Binary Two’s
Complement format, as shown in Table VIII. This table
represents the ideal output code for the given input voltage
and does not include the effects of offset, gain, or noise.
POWER DISSIPATION
There are three power modes for the ADS8343: full-power
(PD1 = PD0 = 1
B
), auto power-down (PD1 = PD0 = 0
B
), and
shutdown (
SHDN LOW). The affects of these modes varies
depending on how the ADS8343 is being operated. For
example, at full conversion rate and 24-clocks per conver-
sion, there is very little difference between full-power mode
and auto power-down, a shutdown (
SHDN LOW) will not
lower power dissipation.
When operating at full-speed and 24 clocks per conversion
(see Figure 6), the ADS8343 spends most of its time acquir-
ing or converting. There is little time for auto power-down,
assuming that this mode is active. Thus, the difference
between full-power mode and auto power-down is negligible.
If the conversion rate is decreased by simply slowing the
frequency of the DCLK input, the two modes remain approxi-
mately equal. However, if the DCLK frequency is kept at the
maximum rate during a conversion, but conversion are sim-
ply done less often, then the difference between the two
modes is dramatic. Figure 10 shows the difference between
reducing the DCLK frequency (“scaling” DCLK to match the
conversion rate) or maintaining DCLK at the highest fre-
quency and reducing the number of conversion per second.
In the later case, the converter spends an increasing per-
centage of its time in power-down mode (assuming the auto
power-down mode is active).
DESCRIPTION ANALOG VALUE
Full-Scale Range 2 • V
REF
Least Significant 2 • V
REF
/65536
Bit (LSB) BINARY CODE HEX CODE
+Full-Scale +V
REF
– 1LSB 0111 1111 1111 1111 7FFF
Midscale 0V 0000 0000 0000 0000 0000
Midscale – 1LSB 0V – 1LSB 1111 1111 1111 1111 FFFF
–Full-Scale –V
REF
1000 0000 0000 0000 8000
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
TABLE VIII. Ideal Input Voltages and Output Codes.
FIGURE 10. Supply Current versus Directly Scaling the Fre-
quency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
10k 100k1k 1M
f
SAMPLE
(Hz)
Supply Current (µA)
100
10
1
1000
f
CLK
= 2.4MHz
f
CLK
= 24 • f
SAMPLE
T
A
= 25°C
+V
CC
= +2.7V
V
REF
= +2.5V
PD1 = PD0 = 0
FIGURE 11. Supply Current vs State of CS .
10k 100k1k 1M
f
SAMPLE
(Hz)
Supply Current (µA)
0.00
0.09
14
0
2
4
6
8
10
12
CS LOW
(GND)
CS HIGH (+V
CC
)
T
A
= 25°C
+V
CC
= +2.7V
V
REF
= +2.5V
f
CLK
= 24 • f
SAMPLE
PD1 = PD0 = 0
If DCLK is active and CS is LOW while the ADS8343 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping
CS HIGH. The differences in
supply current for these two cases are shown in Figure 11.
Operating the ADS8343 in auto power-down mode will result
in the lowest power dissipation, and there is no conversion
time “penalty” on power-up. The very first conversion will be
valid.
SHDN can be used to force an immediate power-down.