Datasheet

5-1

EVM Operation

The analog input source for channels AIN0–AIN3 is applied directly to

connector J1, pins 2, 4, 6, or 8 (top or bottom side) or through the onboard AFE

via the SMA connector labeled INPUT. When using the AFE circuit, resistors

R9, R10, R11 and R12 as well as capacitors C21 and C27 provide

customizable filtering of the input signal. J1 or AFE inputs are selected through

jumpers W1–W4. For J1 use, shunts must be installed at pins 1-2.

The digital control signals are applied directly to J4 (top or bottom side). The

ADS8342 modular EVM can also be connected directly to a DSP,

microcontroller, or FPGA interface board. If an external conversion clock is

required, the clock is applied to the SMA connector labeled EXT CLK in

accordance with the clock division factor (see table in Section 3.1).

The ADS8342 EVM is designed for use with the 5-6K interface board.

Conversions are initiated by writing to the external DSP data bus at an address

determined by jumper settings on the EVM and interface board.

With a proper conversion clock applied the EVM, the ADC responds to a

/CONVST signal (via the processor /WR strobe) and provides the host with an

interrupt via J4 pin 19. The host must then access data from channel A0

through A3 by reading from the appropriate address (see SLAU104 and

SLAA176 for details). When operating in BYTE mode, two successive reads

from the selected analog input channel are required to obtain a full 16 bit data

transfer.

Chapter 5