Datasheet
ADS8341
14
SBAS136D
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 900 ns
t
DS
DIN Valid Prior to DCLK Rising 50 ns
t
DH
DIN Hold After DCLK HIGH 10 ns
t
DO
DCLK Falling to DOUT Valid 100 ns
t
DV
CS Falling to DOUT Enabled 70 ns
t
TR
CS Rising to DOUT Disabled 70 ns
t
CSS
CS Falling to First DCLK Rising 50 ns
t
CSH
CS Rising to DCLK Ignored 0 ns
t
CH
DCLK HIGH 150 ns
t
CL
DCLK LOW 150 ns
t
BD
DCLK Falling to BUSY Rising 100 ns
t
BDV
CS Falling to BUSY Enabled 70 ns
t
BTR
CS Rising to BUSY Disabled 70 ns
The other method is shown in Figure 5, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the DOUT line. BUSY and DOUT go into
a high-impedance state when CS goes high; after the next CS
falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8341 generates its own
conversion clock internally. This relieves the microproces-
sor from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate from 0MHz to 2.0MHz.
BUSY goes LOW at the start of conversion and then returns
HIGH when the conversion is complete. During the conver-
sion, BUSY will remain LOW for a maximum of 8µs. Also,
during the conversion, DCLK should remain LOW to achieve
the best noise performance. The conversion result is stored
in an internal register; the data may be clocked out of this
register any time after the conversion is complete.
If CS is LOW when BUSY goes LOW following a conver-
sion, the next falling edge of the external serial clock will
write out the MSB on the DOUT line. The remaining bits
(D14-D0) will be clocked out on each successive clock cycle
following the MSB. If CS is HIGH when BUSY goes LOW
then the DOUT line will remain in tri-state until CS goes
LOW, as shown in Figure 6. CS does not need to remain
LOW once a conversion has started. Note that BUSY is not
tri-stated when CS goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8341 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time t
ACQ
, is kept above 1.7µs.
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for
the digital interface of the ADS8341.
TABLE VII. Timing Specifications (+V
CC
= +4.75V to
+5.25V, T
A
= –40°C to +85°C, C
LOAD
= 50pF).
t
ACQ
AcquireIdle Conversion
1
DCLK
CS
81
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0
81 8
Idle
18
Zero Filled...
t
ACQ
AcquireIdle Conversion
1
DCLK
CS
8
9 1011121314151617181920212223242526272829303132
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
FIGURE 5. External Clock Mode 32 Clocks Per Conversion.
FIGURE 6. Internal Clock Mode Timing.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 1.5 µs
t
DS
DIN Valid Prior to DCLK Rising 100 ns
t
DH
DIN Hold After DCLK HIGH 10 ns
t
DO
DCLK Falling to DOUT Valid 200 ns
t
DV
CS Falling to DOUT Enabled 200 ns
t
TR
CS Rising to DOUT Disabled 200 ns
t
CSS
CS Falling to First DCLK Rising 100 ns
t
CSH
CS Rising to DCLK Ignored 0 ns
t
CH
DCLK HIGH 200 ns
t
CL
DCLK LOW 200 ns
t
BD
DCLK Falling to BUSY Rising 200 ns
t
BDV
CS Falling to BUSY Enabled 200 ns
t
BTR
CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V to 3.6V,
T
A
= –40°C to +85°C, C
LOAD
= 50pF).