Datasheet
ADS8331
ADS8332
www.ti.com
SBAS363C –DECEMBER 2009–REVISED MAY 2012
TIMING CHARACTERISTICS: VA = 2.7V
At T
A
= –40°C to +85°C, VA = 2.7V, and VBD = 1.65V, unless otherwise noted.
(1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
External, f
CCLK
= 1/2 f
SCLK
0.5 10.5 MHz
f
CCLK
Frequency, conversion clock, CCLK
Internal 10.5 11 12.2 MHz
t
SU1
Setup time, rising edge of CS to EOC
(3)
Read while converting 1 CCLK
t
H1
CS hold time with respect to EOC
(3)
Read while sampling 25 ns
t
WL1
Pulse duration, CONVST low 40 ns
t
WH1
Pulse duration, CS high 40 ns
t
SU2
Setup time, rising edge of CS to EOS Read while sampling 25 ns
t
H2
CS hold time with respect to EOS Read while converting 25 ns
t
SU3
Setup time, falling edge of CS to first falling edge of SCLK 14 ns
t
WL2
Pulse duration, SCLK low 17 t
SCLK
– t
WH2
ns
t
WH2
Pulse duration, SCLK high 12 t
SCLK
– t
WL2
ns
I/O clock only 40 ns
I/O and conversion clocks 47.6 1000 ns
t
SCLK
Cycle time, SCLK
I/O clock, daisy-chain mode 40 ns
I/O and conversion clocks,
47.6 1000 ns
daisy-chain mode
t
D1
Delay time, falling edge of SCLK to SDO invalid 10pF load 8 ns
t
D2
Delay time, falling edge of SCLK to SDO valid 10pF load 35 ns
t
D3
Delay time, falling edge of CS to SDO valid, SDO MSB output 10pF load 35 ns
t
SU4
Setup time, SDI to falling edge of SCLK 8 ns
t
H3
Hold time, SDI to falling edge of SCLK 8 ns
t
D4
Delay time, rising edge of CS to SDO 3-state 10pF load 15 ns
t
SU5
Setup time, last falling edge of SCLK before rising edge of CS 15 ns
t
H4
Hold time, last falling edge of SCLK before rising edge of CS 2 ns
t
SU6
(4)
Setup time, rising edge of SCLK to rising edge of CS 10 ns
t
H5
(4)
Hold time, rising edge of SCLK to rising edge of CS 2 ns
t
D5
Delay time, falling edge of CS to deactivation of INT 10pF load 40 ns
(1) All input signals are specified with t
r
= t
f
= 1.5ns (10% to 90% of VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See the Timing Diagrams section.
(3) The EOC and EOS signals are the inverse of each other.
(4) Applies to the 5th or 17th rising SCLK when sending 4-bit or 16-bit commands, respectively, to the ADS8331/32.
Copyright © 2009–2012, Texas Instruments Incorporated 7