Datasheet

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ADS8331

ADS8332

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SBAS363C –DECEMBER 2009–REVISED MAY 2012

DIGITAL INTERFACE

The serial interface is designed to accommodate the latest high-speed processors with an SCLK frequency of up

to 40MHz (VA = VBD = 5.0V). Each cycle starts with the falling edge of FS/CS. The internal data register

content, which is made available to the output register at the end of conversion, is presented on the SDO output

pin on the falling edge of FS/CS. The first bit is the most significant bit (MSB). The output data bits are valid on

the falling edge of SCLK with the t

delay (see the Timing Characteristics)so that the host processor can read

the data on the falling edge. Serial data input is also read on the falling edge of SCLK.

The complete serial I/O cycle starts after the falling edge of FS/CS and ends 16 falling edges of SCLK later (see

NOTE). The serial interface works with CPOL = '1', CPHA = '0'. This setting means the falling edge of FS/CS

may fall while SCLK is high. The same timing relaxation applies to the rising edge of FS/CS where SCLK may be

high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS.

NOTE

There are cases where a cycle can be anywhere from 4 SCLKs up to 24 SCLKs,

depending on the read mode combination. See Table 4 for details.

Internal Register

The internal register consists of two parts: four bits for the Command register (CMR) and 12 bits for the

Configuration register (CFR).

Table 4. Command Set Defined by Command Register (CMR)

(1)

WAKE UP MINIMUM

FROM AUTO- SCLKs

D[15:12] HEX COMMAND D[11:0] NAP REQUIRED R/W

0000b 0h Select analog input channel 0 Don't care Y 4 W

0001b 1h Select analog input channel 1 Don't care Y 4 W

0010b 2h Select analog input channel 2 Don't care Y 4 W

0011b 3h Select analog input channel 3 Don't care Y 4 W

0100b 4h Select analog input channel 4

(2)

Don't care Y 4 W

0101b 5h Select analog input channel 5

(2)

Don't care Y 4 W

0110b 6h Select analog input channel 6

(2)

Don't care Y 4 W

0111b 7h Select analog input channel 7

(2)

Don't care Y 4 W

1000b 8h Reserved Reserved — — —

1001b 9h Reserved Reserved — — —

1010b Ah Reserved Reserved — — —

1011b Bh Wake up Don't care Y 4 W

1100b Ch Read CFR Don't care — 16 R

1101b Dh Read data Don't care — 16 R

1110b Eh Write CFR CFR Value — 16 W

Default mode

1111b Fh Don't care Y 4 W

(load CFR with default value)

(1) The first four bits from SDO after the falling edge of FS/CS are the four MSBs from the previous conversion result. The next 12 bits from

SDO are the contents of the CFR.

(2) These commands apply only to the ADS8332; they are reserved (not availble) for the ADS8331.