Datasheet

CCLK

CONVST_OUT

(internal)

NAP_ACTIVE

(internal)

EOC

(activelow)

3 19 20 21

42 43

ADS8331

ADS8332

SBAS363C –DECEMBER 2009–REVISED MAY 2012

www.ti.com

The ADS8331/32 can support sampling rates of up to 500kSPS in Auto-Trigger mode. This rate is selectable by

programming the CFR_D8 bit in the Configuration register. In 500kSPS mode, consecutive conversion start

pulses to the analog core are generated 21 conversion clock cycles apart. In 250kSPS mode, consecutive

conversion-start pulses are 42 conversion clock cycles apart. The Nap and Deep Power-Down modes are

available with either sampling rate; however, Auto-Nap mode is available only with a sampling rate of 250kSPS

when Auto-Trigger mode is enabled. The analog core cannot be powered down when the Auto-Nap mode

sampling rate is 500kSPS because at that rate, there is no period of time when the analog core is not actively

being used.

Figure 42 shows the timing diagram for conversion start and auto-nap power-down signals for a 250kSPS

sampling rate in Auto-Trigger mode. For a 16-bit ADC output word, consecutive new conversion start pulses are

generated 2 × (18 + 3) cycles apart. NAP_ACTIVE (the signal to power down the analog core in Nap and Auto-

Nap modes) goes low six (3 + 3) conversion clock cycles before the conversion start falling edge, thus powering

up the analog core. It takes three conversion clock cycles after NAP_ACTIVE goes low to power up the analog

core. The analog core is powered down a cycle after the end of a conversion. For a 16-bit ADC with a 500kSPS

sampling rate and three conversion clock cycle sampling, consecutive conversion start pulses are generated 21

conversion clock cycles apart.

Figure 42. Timing for Conversion Start and Auto-Nap Power-Down Signals in Auto-Trigger Mode

(250kSPS Sampling and Three Conversion Clock Cycles for Acquisition)

Timing diagrams for reading from the ADS8331/32 with various trigger and power-down modes are shown in

Figure 43 through Figure 45. The total (acquisition + conversion) times for the different trigger and power-down

modes are listed in Table 3.

Table 3. Total Acquisition + Conversion Times

MODE ACQUISITION + CONVERSION TIME

Auto-Trigger at 500kSPS = 21 CCLK

Manual-Trigger ≥ 21 CCLK

Manual-Trigger with Deep Power-Down ≥ 4 SCLK + 1μs + 3 CCLK + 18 CCLK + 16 SCLK + 2μs

Manual-Trigger with Nap Power-Down ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK + 200ns

≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200ns (using wakeup to resume)

Manual-Trigger with Auto-Nap Power-Down

≥ 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200ns (using CONVST to resume)