Datasheet

TIMING CHARACTERISTICS
ADS8329
ADS8330
www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009
All specifications typical at – 40 ° C to 85 ° C, +VA = 2.7 V, +VBD = 1.8 V (unless otherwise noted)
(1) (2)
PARAMETER MIN TYP MAX UNIT
External, 3 V ≤ +VA ≤ 3.6 V,
0.5 21
f
CCLK
= 1/2 f
SCLK
External, 2.7 V ≤ +VA ≤ 3 V,
f
CCLK
Frequency, conversion clock, CCLK 0.5 18.9 MHz
f
CCLK
= 1/2 f
SCLK
Internal,
20 22.3 23.5
f
CCLK
= 1/2 f
SCLK
t
su(CSF-EOC)
Setup time, falling edge of CS to EOC 1 CCLK
t
h(CSF-EOC)
Hold time, falling edge of CS to EOC 0 ns
t
wL(CONVST)
Pulse duration, CONVST low 40 ns
t
su(CSF-EOS)
Setup time, falling edge of CS to EOS 20 ns
t
h(CSF-EOS)
Hold time, falling edge of CS to EOS 20 ns
t
su(CSR-EOS)
Setup time, rising edge of CS to EOS 20 ns
t
h(CSR-EOS)
Hold time, rising edge of CS to EOS 20 ns
Setup time, falling edge of CS to first
t
su(CSF-SCLK1F)
5 ns
falling SCLK
t
wL(SCLK)
Pulse duration, SCLK low 8 t
c(SCLK)
– 8 ns
t
wH(SCLK)
Pulse duration, SCLK high 8 t
c(SCLK)
– 8 ns
All modes,
23.8 2000
3 V ≤ +VA ≤ 3.6 V
t
c(SCLK)
Cycle time, SCLK ns
All modes,
26.5 2000
2.7 V ≤ +VA < 3 V
Delay time, falling edge of SCLK to SDO
t
d(SCLKF-SDOINVALID)
10-pF Load 7.5 ns
invalid
Delay time, falling edge of SCLK to SDO
t
d(SCLKF-SDOVALID)
10-pF Load 16 ns
valid
10-pF Load,
13
2.7 V ≤ +VA ≤ 3 V
Delay time, falling edge of CS to SDO
t
d(CSF-SDOVALID)
ns
valid, SDO MSB output
10-pF Load,
11
3 V ≤ +VA ≤ 3.6 V
t
su(SDI-SCLKF)
Setup time, SDI to falling edge of SCLK 8 ns
t
h(SDI-SCLKF)
Hold time, SDI to falling edge of SCLK 4 ns
Delay time, rising edge of CS/FS to SDO
t
d(CSR-SDOZ)
8 ns
3-state
Setup time, 16th falling edge of SCLK
t
su(16th SCLKF-CSR)
10 ns
before rising edge of CS/FS
Delay time, CDI high to SDO high in
t
d(SDO-CDI)
10-pF Load, chain mode 23 ns
daisy chain mode
(1) All input signals are specified with t
r
= t
f
= 1.5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See timing diagrams.
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