Datasheet

ADS8329
#1
SDI
SDO
ADS8329
#2
SDI
SDO
ADS8329
#3
SDI
SDO
MicroController
SDISDOGPIO1 GPIO2 GPIO3
Programdevice#1CFR_D[7:5]=XX0b
INT
CS
CONVST
CS
CONVST
CS
CONVST
EOC/INT
CDI CDI
Programdevice#2and#3CFR_D[7:5]=XX1b
SCLK
SCLKSCLK SCLK
CONVST #1,
CONVST
CONVST
#2,
#3
EOC#1
(activelow)
INT #3
(active low)
CS/FS#2,
/FS#3CS
SCLK#1,
SCLK#2,
SCLK#3
SDO#1,
CDI#2
SDO#2,
CDI#3
SDO#3
SDI#1,
SDI#2,
SDI#3
CONFIGURE
READResult READResult
EOS
EOC
EOS
Nth
Nthfrom#1
Nthfrom#1 Nthfrom#1N − 1thfrom#2
Nthfrom#3 N − 1thfrom#2 Nthfrom#1
1110............ 1101b
1101b
1 ..................16
Cascaded ManualTrigger/ReadWhileSampling
(Use internalCCLK,EOCactivelow,and activelow)heldINT CS
low duringtheNtimes16bitstransfercycle.
Hi-Z Hi-Z
Hi-Z
Hi-Z
1 ..................16 1..................16
Hi-Z
Hi-Z
CS/FS#1
t
CONV
=18CCLKs
t
d(SDO-CDI)
t
SAMPLE1
=3CCLKsmin
t
d(CSR-EOS)
=20nsmin
t
d(CSR-EOS)
=20nsmin
t
d(SDO-CDI)
ADS8329
ADS8330
www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009
Figure 59. Multiple Converters Connected Using Chain Mode
When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest
of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the
CDI input data goes straight to the output register, therefore the serial input data passes through the converter
with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for
detailed timing. In this timing the conversion in each converters are done simultaneously.
Figure 60. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS
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