Datasheet

UndefinedZone
0.400
0.125
AVDD(V)
t(s)
5.500
5.000
4.000
3.000
2.700
2.000
1.000
0
1.500
SpecifiedSupply
VoltageRange
POR
TriggerLevel
0.350
ADS8329
ADS8330
www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009
When the device is powered up, the POR sets the device to default mode when AVDD reaches 1.5V. When the
device is powered down, the POR circuit requires AVDD to remain below 125mV for at least 350ms to ensure
proper discharging of internal capacitors and to correct the behavior of the ADC when powered up again. If
AVDD drops below 400mV but remains above 125mV, the internal POR capacitor does not discharge fully and
the device requires a software reset to perform correctly after the recovery of AVDD (this condition is shown as
the undefined zone in Figure 65 ).
Figure 65. Relevant Voltage Levels for POR
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): ADS8329 ADS8330