Datasheet

Logic
Delay
< = 8 .3 ns
ADS 8327 # 3
QD
CLK
Logic
Delay
< = 8 .3 ns
ADS 8327 # 2
QD
CLK
Logic
Delay
< = 8 .3 ns
ADS 8327 # 1
QD
CLK
SCLKinput
SDO
SDO
SDO
CDI
CDI
CDI
Serialdata
input
Serialdata
output
Logic
Delay
PlusPAD
2.7ns
Logic
Delay
PlusPAD
2.7ns
Logic
Delay
PlusPAD
8.3ns
Logic
Delay
PlusPAD
8.3ns
Logic
Delay
PlusPAD
2.7ns
Logic
Delay
PlusPAD
8.3ns
Intermediate
Latch
SAR Shift
Register
Output
Register
Conversion Clock
SW RESET
POR
SET
Latched by Falling Edge of CS
Latched by End Of
Conversion
EOC
SDO
SCLK
CS
EOC
CDI
ADS8327
ADS8328
SLAS415E – APRIL 2006– REVISED JANUARY 2011 www.ti.com
SCLK skew between converters and data path delay through the converters configured in chain mode can affect
the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be
necessary to slow down the SCLK when the devices are configured in chain mode.
Figure 63. Typical Delay Through Converters Configured in Chain Mode
RESET
The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR_D0. These
two mechanisms are NOR-ed internally. When a reset (software or POR) is issued, all register data are set to the
default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state
machine is reset to the power-on state.
Figure 64. Digital Output Under Reset Condition
36 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8327 ADS8328