Datasheet

Note:olddatashown.
CONFIGURE
READResult READResult
EOS
EOC EOS
Nth
Nthfrom#1
Nthfrom#1
Nthfrom#1
N − 1thfrom#2
Nthfrom#3
N − 1thfrom#2
1110............ 1101b
1101b
1..................16
1 ..................16 1..................16
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Cascaded ManualTrigger/ReadWhileSampling
(UseinternalCCLK,EOCactivelowand activelow)
heldlowduringtheNtimes16bitstransfercycle.
INT
CS
CONVST #1,
CONVST #3
CONVST #2=1
EOC#1
(activelow)
INT #1
(active low)
SCLK#1,
SCLK#2,
SCLK#3
SDO#1,
CDI#2
SDO#2,
CDI#3
SDO#3
SDI#1,
SDI#2,
SDI#3
CS/FS#1
CS/FS#2,
CS/FS#3
t
CONV
=18CCLKs
t
SAMPLE1
=3CCLKsmin
t
d(CSR-EOS)
=20nsmin
t
d(CSR-EOS)
=20nsmin
t
d(SDO-CDI)
t
d(SDO-CDI)
ADS8327
ADS8328
www.ti.com SLAS415E – APRIL 2006– REVISED JANUARY 2011
Figure 62. Simplified Cascade Timing (Separate CONVST)
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
bit, chain mode, and the way a channel is selected, i.e., auto channel select. This is listed in Table 7.
Table 7. Required SCLKs For Different Read Out Mode Combinations
CHAIN MODE AUTO CHANNEL NUMBER OF SCLK PER SPI
TAG ENABLED CFR.D1 TRAILING BITS
ENABLED CFR.D5 SELECT CFR.D11 READ
0 0 0 16 None
0 0 1 ≥17 MSB is TAG bit plus zero(s)
0 1 0 16 None
0 1 1 ≥17 TAG bit plus 7 zeros
1 0 0 16 None
1 0 1 24 TAG bit plus 7 zeros
1 1 0 16 None
1 1 1 24 TAG bit plus 7 zeros
© 2006–2011, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): ADS8327 ADS8328