Datasheet

CONVST #1,
CONVST
CONVST
#2,
#3
EOC#1
(activelow)
INT #3
(active low)
CS/FS#2,
/FS#3CS
SCLK#1,
SCLK#2,
SCLK#3
SDO#1,
CDI#2
SDO#2,
CDI#3
SDO#3
SDI#1,
SDI#2,
SDI#3
CONFIGURE
READResult READResult
EOS
EOC
EOS
Nth
Nthfrom#1
Nthfrom#1 Nthfrom#1Nthfrom#2
Nthfrom#3 Nthfrom#2 Nthfrom#1
1110............ 1101b
1101b
1 ..................16
Cascaded ManualTrigger/ReadWhileSampling
(Use internalCCLK,EOCactivelow,and activelow)heldINT CS
low duringtheNtimes16bitstransfercycle.
Hi-Z Hi-Z
Hi-Z
Hi-Z
1 ..................16 1..................16
Hi-Z
Hi-Z
CS/FS#1
t
CONV
=18CCLKs
t
d(SDO-CDI)
t
SAMPLE1
=3CCLKsmin
t
d(CSR-EOS)
=20nsmin
t
d(CSR-EOS)
=20nsmin
t
d(SDO-CDI)
ADS8327
ADS8328
www.ti.com SLAS415E – APRIL 2006– REVISED JANUARY 2011
When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest
of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the
CDI input data goes straight to the output register, therefore the serial input data passes through the converter
with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for
detailed timing. In this timing the conversion in each converters are done simultaneously.
Figure 60. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS
Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The
different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters).
The first 16-bit word after the falling chip select is always the data from the chip that received the chip select
signal.
Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and so
on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example, the
same data from the converter is going to be shown repeatedly.
Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the same
data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired result.
© 2006–2011, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): ADS8327 ADS8328