Datasheet

ADS8327
ADS8328
www.ti.com SLAS415E – APRIL 2006– REVISED JANUARY 2011
READING THE CONFIGURATION REGISTER
The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is
similar to reading a conversion result except CONVST is not used and there is no activity on the EOC/INT pin.
The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents.
Table 5. Configuration Register (CFR) Map
SDI BIT
DEFINITION
CFR – D[11 – 0]
Channel select mode
D11 Default = 1
0: Manual channel select enabled. Use channel select commands to 1: Auto channel select enabled. All channels are sampled and
access a different channel. converted sequentially until the cycle after this bit is set to 0.
Conversion clock (CCLK) source select
D10 Default = 1
0: Conversion clock (CCLK) = SCLK/2 1: Conversion clock (CCLK) = Internal OSC
Trigger (conversion start) select: start conversion at the end of sampling (EOS). If D9 = 0, the D4 setting is ignored.
D9 Default = 1
0: Auto trigger automatically starts (4 internal clocks after EOC inactive) 1: Manual trigger manually started by falling edge of CONVST
D8 Default = 0 Don't care Don't care
Pin 10 polarity select when used as an output (EOC/INT)
D7 Default = 1
0: EOC Active high/INT active high 1: EOC Active low/INT active low
Pin 10 function select when used as an output (EOC/INT)
D6 Default = 1
0: Pin used as INT 1: Pin used as EOC
Pin 10 I/O select for chain mode operation
D5 Default = 1
0: Pin 10 is used as CDI input (chain mode enabled) 1: Pin 10 is used as EOC/INT output
Auto nap power-down enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0.
D4 Default = 1
0: Auto nap power-down enabled (not activated) 1: Auto nap power-down disabled
Nap power-down (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command.
D3 Default = 1
0: Enable/activate device in nap power-down 1: Remove device from nap power-down (resume)
Deep power-down. This bit is set to 1 automatically by wake-up command.
D2 Default = 1
0: Enable/activate device in deep power-down 1: Remove device from deep power-down (resume)
D1 Default = TAG bit enable. This bit is ignored by the ADS8327 and is always read 0.
0: ADS8327
0: TAG bit disabled. 1: TAG bit output enabled. TAG bit appears at the 17th SCLK.
1: ADS8328
Reset
D0 Default = 1
0: System reset 1: Normal operation
READING CONVERSION RESULT
The conversion result is available to the input of the output data register (ODR) at EOC and presented to the
output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out
via the SDO pin any time except during the quiet zone. This is 20 ns before and 20 ns after the end of sampling
(EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when manual trigger is used or
the end of the 3rd conversion clock (CCLK) after EOC if auto trigger is used.
The falling edge of FS/CS should not be placed at the precise moment (minimum of at least one conversion
clock (CCLK) delay) at the end of a conversion (by default when EOC goes high), otherwise the data are corrupt.
If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placed after
the end of a conversion, the current conversion result is read.
The conversion result is 16-bit data in straight binary format as shown in Table 5. Generally 16 SCLKs are
necessary, but there are exceptions where more than 16 SCLKS are required (see Table 7). Data output from
the serial output (SDO) is left adjusted MSB first. The trailing bits are filled with the TAG bit first (if enabled) plus
all zeros. SDO remains low until FS/CS is brought high again.
SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output.
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