Datasheet

ADS8327
ADS8328
SLAS415E – APRIL 2006– REVISED JANUARY 2011 www.ti.com
Internal Register
The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration
data register (CFR).
Table 4. Command Set Defined by Command Register (CMR)
(1)
WAKE UP FROM MINIMUM SCLKs
D[15:12] HEX COMMAND D[11:0] R/W
AUTO NAP REQUIRED
0000b 0h Select analog input channel 0
(2)
Don't care Y 4 W
0001b 1h Select analog input channel 1
(2)
Don't care Y 4 W
0010b 2h Reserved Reserved – – –
0011b 3h Reserved Reserved – – –
0100b 4h Reserved Reserved – – –
0101b 5h Reserved Reserved – – –
0110b 6h Reserved Reserved – – –
0111b 7h Reserved Reserved – – –
1000b 8h Reserved Reserved – – –
1001b 9h Reserved Reserved – – –
1010b Ah Reserved Reserved – – –
1011b Bh Wake up Don't care Y 4 W
1100b Ch Read CFR Don't care – 16 R
1101b Dh Read data Don't care – 16 R
1110 Eh Write CFR CFR Value – 16 W
1111b Fh Default mode (load CFR with default value) Don't care Y 4 W
(1) When SDO is not in 3-state (FS/CS low and SCLK running), the bits from SDO are always part (depending on how many SCLKs are
supplied) of the previous conversion result.
(2) These two commands apply to the ADS8328 only.
WRITING TO THE CONVERTER
There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR
plus CFR. The command set is listed in Table 4. A simple command requires only 4 SCLKs and the write takes
effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 7 for exceptions
that require more than 16 SCLKs).
Configuring the Converter and Default Mode
The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A
write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the fourth
falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK.
A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least
four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of
SCLK.
CFR default values are all 1s (except for CFR_D1, this bit is ignored by the ADS8327 and is always read as a 0).
The same default values apply for the CFR after a power-on reset (POR) and SW reset.
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