Datasheet

ADS8326
SBAS343C MAY 2007REVISED SEPTEMBER 2009..................................................................................................................................................
www.ti.com
LAYOUT resistor can help in this case). Keep in mind that
while the ADS8326 draws very little current from the
For optimum performance, care should be taken with
reference on average, there are still instantaneous
the physical layout of the ADS8326 circuitry. This is
current demands placed on the external input and
particularly true if the reference voltage is low and/or
reference circuitry.
the conversion rate is high. At a 250kHz conversion
rate, the ADS8326 makes a bit decision every 167ns. Texas Instruments' OPA365 op amp provides
That is, for each subsequent bit decision, the digital optimum performance for buffering the signal inputs;
output must be updated with the results of the last bit the OPA350 can be used to effectively buffer the
decision, the capacitor array appropriately switched reference input.
and charged, and the input to the comparator settled
Also, keep in mind that the ADS8326 offers no
to a 16-bit level, all within one clock cycle.
inherent rejection of noise or voltage variation in
The basic SAR architecture is sensitive to spikes on regards to the reference input. This is of particular
the power supply, reference, and ground connections concern when the reference input is tied to the power
that occur just prior to latching the comparator output. supply. Any noise and ripple from the supply will
Thus, during any single conversion for an n-bit SAR appear directly in the digital results. While
converter, there are n windows in which large high-frequency noise can be filtered out, as described
external transient voltages can easily affect the in the previous paragraph, voltage variation resulting
conversion result. Such spikes might originate from from the line frequency (50Hz or 60Hz) can be
switching power supplies, digital logic, and difficult to remove.
high-power devices, to name a few potential sources.
The GND pin on the ADS8326 should be placed on a
This particular source of error can be very difficult to
clean ground point. In many cases, this will be the
track down if the glitch is almost synchronous to the
analog ground. Avoid connecting the GND pin too
converter DCLOCK signal because the phase
close to the grounding point for a microprocessor,
difference between the two changes with time and
microcontroller, or digital signal processor. If needed,
temperature, causing sporadic misoperation.
run a ground trace directly from the converter to the
With this in mind, power to the ADS8326 should be power-supply connection point. The ideal layout will
clean and well-bypassed. A 0.1μF ceramic bypass include an analog ground plane for the converter and
capacitor should be placed as close as possible to associated analog circuitry.
the ADS8326 package. In addition, a 1μF to 10μF
capacitor and a 5 or 10 series resistor may be
used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a
47μF capacitor. Again, a series resistor and large
capacitor can be used to low-pass filter the reference
voltage. If the reference voltage originates from an op
amp, make sure that the op amp can drive the
bypass capacitor without oscillation (the series
26 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8326