Datasheet

ADS8326
www.ti.com
.................................................................................................................................................. SBAS343C MAY 2007REVISED SEPTEMBER 2009
Short Cycling
POWER DISSIPATION
Another way to save power is to use the CS signal to
The architecture of the converter, the semiconductor
short-cycle the conversion. The ADS8326 places the
fabrication process, and a careful design allow the
latest data bit on the D
OUT
line as it is generated;
ADS8326 to convert at up to a 250kHz rate while
therefore, the converter can easily be short-cycled.
requiring very little power. However, for the absolute
This term means that the conversion can be
lowest power dissipation, there are several things to
terminated at any time. For example, if only 14 bits of
keep in mind.
the conversion result are needed, then the conversion
The power dissipation of the ADS8326 scales directly
can be terminated (by pulling CS high) after the 14th
with conversion rate. Therefore, the first step to
bit has been clocked out.
achieving the lowest power dissipation is to find the
This technique can also be used to lower the power
lowest conversion rate that will satisfy the
dissipation (or to increase the conversion rate) in
requirements of the system.
those applications where an analog signal is being
In addition, the ADS8326 goes into Power-Down
monitored until some condition becomes true. For
mode under two conditions: when the conversion is
example, if the signal is outside a predetermined
complete and whenever CS is high (see the Timing
range, the full 16-bit conversion result may not be
Information section). Ideally, each conversion should
needed. If so, the conversion can be terminated after
occur as quickly as possible, preferably at a 6.0MHz
the first n bits, where n might be as low as 3 or 4.
clock rate. This way, the converter spends the
This results in lower power dissipation in both the
longest possible time in Power-Down mode. This is
converter and the rest of the system because they
very important because the converter not only uses
spend more time in Power-Down mode.
power on each DCLOCK transition (as is typical for
digital CMOS components), but also uses some
POWER-ON RESET
current for the analog circuitry, such as the
comparator. The analog section dissipates power The ADS8326 bias circuit is self-starting. There may
continuously until Power-Down mode is entered. be a static current (approximately 1.5mA with V
DD
=
5V) after power-on, unless the circuit is powered
Figure 17 and Figure 18 (+5V), and Figure 35 and
down. It is recommended to run a single test
Figure 36 illustrate the current consumption of the
conversion (configured the same as any regular
ADS8326 versus sample rate. For these graphs, the
conversion) after the power supply reaches at least
converter is clocked at maximum speed regardless of
2.4V to ensure the device is put into power-down
the sample rate. CS is held high during the remaining
mode.
sample period.
There is an important distinction between the
power-down mode that is entered after a conversion
is complete and the full power-down mode that is
enabled when CS is high. CS low will only shut down
the analog section. The digital section is completely
shut down only when CS is high. Thus, if CS is left
low at the end of a conversion, and the converter is
continually clocked, the power consumption will not
be as low as when CS is high.
Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): ADS8326