Datasheet
ADS8326
www.ti.com
.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
THEORY OF OPERATION
The ADS8326 is a classic Successive Approximation The external clock can vary between 24kHz (1kHz
Register (SAR) Analog-to-Digital (A/D) converter. The throughput) and 6.0MHz (250kHz throughput). The
architecture is based on capacitive redistribution that duty cycle of the clock is essentially unimportant, as
inherently includes a sample-and-hold function. The long as the minimum high and low times are at least
converter is fabricated on a 0.6μ CMOS process. The 200ns (V
DD
= 4.75V or greater). The minimum clock
architecture and process allow the ADS8326 to frequency is set by the leakage on the internal
acquire and convert an analog signal at up to capacitors to the ADS8326.
250,000 conversions per second while consuming
The analog input is provided to two input pins: +IN
less than 10mW from V
DD
.
and –IN. When a conversion is initiated, the
Differential linearity for the ADS8326 is differential input on these pins is sampled on the
factory-adjusted via a package-level trim procedure. internal capacitor array. While a conversion is in
The state of the trim elements is stored in non-volatile progress, both inputs are disconnected from any
memory and is continuously updated after each internal function.
acquisition cycle, just prior to the start of the
The digital result of the conversion is clocked out by
successive approximation operation. This process
the DCLOCK input and is provided serially (most
ensures that one complete conversion cycle always
significant bit first) on the D
OUT
pin.
returns the part to its factory-adjusted state in the
event of a power interruption.
The digital data that is provided on the D
OUT
pin is for
the conversion currently in progress–there is no
The ADS8326 requires an external reference, an
pipeline delay. It is possible to continue to clock the
external clock, and a single power source (V
DD
). The
ADS8326 after the conversion is complete and to
external reference can be any voltage between 0.1V
obtain the serial data least significant bit first. See the
and V
DD
. The value of the reference voltage directly
Timing Information section for more information.
sets the range of the analog input. The reference
input current depends on the conversion rate of the
ADS8326.
Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): ADS8326