Datasheet

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LAYOUT
ADS8325
SBAS226C – MARCH 2002 – REVISED AUGUST 2007
resistor can help in this case). Keep in mind that
while the ADS8325 draws very little current from the
For optimum performance, care should be taken with
reference on average, there are still instantaneous
the physical layout of the ADS8325 circuitry. This will
current demands placed on the external input and
be particularly true if the reference voltage is low
reference circuitry.
and/or the conversion rate is high. At a 100kHz
conversion rate, the ADS8325 makes a bit decision Texas Instruments' OPA627 op amp provides
every 416ns. That is, for each subsequent bit optimum performance for buffering both the signal
decision, the digital output must be updated with the and reference inputs. For low-cost, low-voltage,
results of the last bit decision, the capacitor array single-supply applications, the OPA2350 or OPA2340
appropriately switched and charged, and the input to dual op amps are recommended.
the comparator settled to a 16-bit level all within one
Also, keep in mind that the ADS8325 offers no
clock cycle.6
inherent rejection of noise or voltage variation in
The basic SAR architecture is sensitive to spikes on regards to the reference input. This is of particular
the power supply, reference, and ground connections concern when the reference input is tied to the power
that occur just prior to latching the comparator output. supply. Any noise and ripple from the supply will
Thus, during any single conversion for an n-bit SAR appear directly in the digital results. While
converter, there are n windows in which large high-frequency noise can be filtered out as described
external transient voltages can easily affect the in the previous paragraph, voltage variation due to
conversion result. Such spikes might originate from the line frequency (50Hz or 60Hz) can be difficult to
switching power supplies, digital logic, and remove.
high-power devices, to name a few. This particular
The GND pin on the ADS8325 should be placed on a
source of error can be very difficult to track down if
clean ground point. In many cases, this will be the
the glitch is almost synchronous to the converter's
analog ground. Avoid connecting the GND pin too
DCLOCK signal as the phase difference between the
close to the grounding point for a microprocessor,
two changes with time and temperature, causing
microcontroller, or digital signal processor. If needed,
sporadic misoperation.
run a ground trace directly from the converter to the
With this in mind, power to the ADS8325 should be power-supply connection point. The ideal layout will
clean and well-bypassed. A 0.1 μ F ceramic bypass include an analog ground plane for the converter and
capacitor should be placed as close as possible to associated analog circuitry.
the ADS8325 package. In addition, a 1 μ F to 10 μ F
capacitor and a 5 Ω or 10 Ω series resistor may be
used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a
47 μ F capacitor. Again, a series resistor and large
capacitor can be used to low-pass filter the reference
voltage. If the reference voltage originates from an op
amp, make sure that the op amp can drive the
bypass capacitor without oscillation (the series
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