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POWER DISSIPATION
1000
100
10
1
Current( A)m
10 100
SampleRate(kHz)
POWERSUPPLYANDREFERENCE
CURRENTvsSAMPLERATE
T
A
=25°C
V =5.0V
DD
V =5.0V
REF
F =2.4MHz
CLK
I
REF
I
DD
1000
100
10
1
Current( A)m
10 100
SampleRate(kHz)
POWERSUPPLYANDREFERENCE
CURRENTvsSAMPLERATE
T
A
=25°C
V =2.7V
DD
V =2.5V
REF
F =2.4MHz
CLK
I
REF
I
DD
SHORT CYCLING
ADS8325
SBAS226C – MARCH 2002 – REVISED AUGUST 2007
The architecture of the converter, the semiconductor
fabrication process, and a careful design, allow the
ADS8325 to convert at up to a 100kHz rate while
requiring very little power. However, for the absolute
lowest power dissipation, there are several things to
keep in mind.
The power dissipation of the ADS8325 scales directly
with conversion rate. Therefore, the first step to
achieving the lowest power dissipation is to find the
lowest conversion rate that will satisfy the
requirements of the system.
In addition, the ADS8325 is in power-down mode
under two conditions: when the conversion is
complete and whenever CS is HIGH (see the Timing
Information section). Ideally, each conversion should
Figure 37. Power-Supply and Reference Current
occur as quickly as possible, preferably at a 2.4MHz
vs Sample Rate at V
DD
= 5V
clock rate. This way, the converter spends the
longest possible time in the power-down mode. This
is very important as the converter not only uses
power on each DCLOCK transition (as is typical for
digital CMOS components), but also uses some
current for the analog circuitry, such as the
comparator. The analog section dissipates power
continuously until the power-down mode is entered.
See Figure 37 and Figure 38 for the current
consumption of the ADS8325 versus sample rate. For
these graphs, the converter is clocked at 2.4MHz
regardless of the sample rate. CS is held HIGH
during the remaining sample period.
There is an important distinction between the
power-down mode that is entered after a conversion
is complete and the full power-down mode that is
enabled when CS is HIGH. CS LOW will shut down
only the analog section. The digital section is
completely shut down only when CS is HIGH. Thus, if
Figure 38. Power-Supply and Reference Current
CS is left LOW at the end of a conversion, and the
vs Sample Rate at V
DD
= 2.7V
converter is continually clocked, the power
consumption will not be as low as when CS is HIGH.
This technique can be used to lower the power
dissipation (or to increase the conversion rate) in
those applications where an analog signal is being
Another way to save power is to utilize the CS signal
monitored until some condition becomes true. For
to short cycle the conversion. Due to the ADS8325
example, if the signal is outside a predetermined
placing the latest data bit on the D
OUT
line as it is
range, the full 16-bit conversion result may not be
generated, the converter can easily be short cycled.
needed. If so, the conversion can be terminated after
This term means that the conversion can be
the first n bits, where n might be as low as 3 or 4.
terminated at any time. For example, if only 14 bits of
This results in lower power dissipation in both the
the conversion result are needed, then the conversion
converter and the rest of the system as they spend
can be terminated (by pulling CS HIGH ) after the
more time in power-down mode.
14th bit has been clocked out.
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