Datasheet

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AVERAGING SERIAL INTERFACE
DIGITAL INTERFACE
SIGNAL LEVELS
DATA FORMAT
ADS8325
SBAS226C – MARCH 2002 – REVISED AUGUST 2007
The noise of the A/D converter can be compensated The ADS8325 communicates with microprocessors
by averaging the digital codes. By averaging and other digital systems via a synchronous 3-wire
conversion results, transition noise will be reduced by serial interface, as illustrated in the Timing
a factor of 1/ √ n, where n is the number of averages. Information section. The DCLOCK signal
For example, averaging four conversion results will synchronizes the data transfer with each bit being
reduce the transition noise from ± 0.5LSB to transmitted on the falling edge of DCLOCK. Most
± 0.25LSB. Averaging should only be used for input receiving systems will capture the bitstream on the
signals with frequencies near DC. rising edge of DCLOCK. However, if the minimum
hold time for D
OUT
is acceptable, the system can use
For AC signals, a digital filter can be used to
the falling edge of DCLOCK to capture each bit.
low-pass filter and decimate the output codes. This
works in a similar manner to averaging; for every A falling CS signal initiates the conversion and data
decimation by 2, the signal-to-noise ratio will improve transfer. The first 4.5 to 5.0 clock periods of the
3dB. conversion cycle are used to sample the input signal.
After the fifth falling DCLOCK edge, D
OUT
is enabled
and will output a LOW value for one clock period. For
the next 16 DCLOCK periods, D
OUT
will output the
conversion result, most significant bit first. After the
least significant bit (B0) has been output, subsequent
The ADS8325 has a wide range of power-supply
clocks will repeat the output data, but in a least
voltage. The A/D converter, as well as the digital
significant bit first format.
interface circuit, is designed to accept and operate
After the most significant bit (B15) has been
from 2.7V up to 5.5V. This voltage range will
repeated, D
OUT
will tri-state. Subsequent clocks will
accommodate different logic levels.
have no effect on the converter. A new conversion is
When the ADS8325's power-supply voltage is in the
initiated only when CS has been taken HIGH and
range of 4.5V to 5.5V (5V logic level), the ADS8325
returned LOW.
can be connected directly to another 5V CMOS
integrated circuit.
Another possibility is that the ADS8325's
The output data from the ADS8325 is in Straight
power-supply voltage is in the range of 2.7V to 3.6V.
Binary format (see Figure 36 . This figure represents
The ADS8325 can be connected directly to another
the ideal output code for a given input voltage and
3.3V LVCMOS integrated circuit.
does not include the effects of offset, gain error, or
noise.
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