Datasheet
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2 3 4
5
6
V (V)
REF
Common-ModeVoltageRange(V)
-1
0
1
-0.3
0.5
4.8
2.5
V =5V
DD
60
50
40
30
20
10
0
-10
DeltaRelativetoV =0V(LSB)
CM
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
V (V)
CM
V =5V
DD
V =4V
REF
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
V (V)
CM
30
20
10
0
-10
-20
DeltaRelativetoV =0V(LSBS)
CM
CHANGEINUPOvsCOMMON-MODEVOLTAGE
V =5V
DD
V =4V
REF
ADS8325
SBAS226C – MARCH 2002 – REVISED AUGUST 2007
The input current required by the analog inputs
depends on a number of factors: sample rate, input
voltage, source impedance, and power-down mode.
Essentially, the current into the ADS8325 charges the
internal capacitor array during the sample period.
After this capacitance has been fully charged, there is
no further input current. The source of the analog
input voltage must be able to charge the input
capacitance (40pF) to a 16-bit settling level within 4.5
clock cycles (1.875 μ s). When the converter goes into
the hold mode, or while it is in the power-down mode,
the input impedance is greater than 1G Ω .
Care must be taken regarding the absolute analog
input voltage. To maintain the linearity of the
Figure 28. +IN Analog Input: Common-Mode
converter, the – IN input should not drop below GND –
Voltage Range vs V
REF
0.3V or exceed GND + 0.5V. The +IN input should
always remain within the range of GND – 0.3V to V
DD
+ 0.3V, or – IN to – IN + V
REF
, whichever limit is
reached first. Outside of these ranges, the converter's
linearity may not meet specifications.
To minimize noise, low bandwidth input signals with
lowpass filters should be used. In each case, care
should be taken to ensure that the output impedance
of the sources driving the +IN and – IN inputs are
matched. Often, a small capacitor (20pF) between the
positive and negative inputs helps to match their
impedance. To obtain maximum performance from
the ADS8325, the input circuit from Figure 31 is
recommended.
Figure 29. Change in Gain vs Common-Mode
Voltage
Figure 30. Change in Unipolar Offset vs
Common-Mode Voltage
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