Datasheet

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THEORY OF OPERATION ANALOG INPUT
ADS8325
0Vto+V
REF
Peak-to-Peak
Common-Mode
Voltage
Common-ModeVoltage +V
REF
+V
REF
t
+IN
Common-Mode Voltage
-IN=Common-ModeVoltage
ADS8325
SBAS226C – MARCH 2002 – REVISED AUGUST 2007
The ADS8325 is a classic Successive Approximation The analog input of ADS8325 is differential. The +IN
Register (SAR) Analog-to-Digital (A/D) converter. The and – IN input pins allow for a differential input signal.
architecture is based on capacitive redistribution that The amplitude of the input is the difference between
inherently includes a sample-andhold function. The the +IN and – IN input, or (+IN) – ( – IN). Unlike some
converter is fabricated on a 0.6 μ CMOS process. The converters of this type, the – IN input is not resampled
architecture and process allow the ADS8325 to later in the conversion cycle. When the converter
acquire and convert an analog signal at up to goes into the hold mode or conversion, the voltage
100,000 conversions per second while consuming difference between +IN and – IN is captured on the
less than 4.5mW from +V
DD
. internal capacitor array.
The ADS8325 requires an external reference, an The range of the – IN input is limited to – 0.3V to
external clock, and a single power source (V
DD
). The +0.5V. Due to this, the differential input could be used
external reference can be any voltage between 2.5V to reject signals that are common to both inputs in the
and 5.5V. The value of the reference voltage directly specified range. Thus, the – IN input is best used to
sets the range of the analog input. The reference sense a remote signal ground that may move slightly
input current depends on the conversion rate of the with respect to the local ground potential.
ADS8325.
The general method for driving the analog input of the
The external clock can vary between 24kHz (1kHz ADS8325 is shown in Figure 26 and Figure 27 . The
throughput) and 2.4MHz (100kHz throughput). The – IN input is held at the common-mode voltage. The
duty cycle of the clock is essentially unimportant as +IN input swings from – IN (or common-mode voltage)
long as the minimum high and low times are at least to – IN + V
REF
(or commonmode voltage + V
REF
), and
200ns (V
DD
= 4.75V or greater). The minimum clock the peak-to-peak amplitude is +V
REF
. The value of
frequency is set by the leakage on the internal V
REF
determines the range over which the
capacitors to the ADS8325. common-mode voltage may vary (see Figure 28 ).
Figure 29 and Figure 30 illustrate the typical change
The analog input is provided to two input pins: +IN
in gain and offset as a function of the common-mode
and – IN. When a conversion is initiated, the
voltage applied to the – IN pin.
differential input on these pins is sampled on the
internal capacitor array. While a conversion is in
progress, both inputs are disconnected from any
internal function.
The digital result of the conversion is clocked out by
the DCLOCK input and is provided serially, most
significant bit first, on the D
OUT
pin. The digital data
that is provided on the D
OUT
pin is for the conversion
currently in progress — there is no pipeline delay. It is
Figure 26. Methods of Driving the ADS8325
possible to continue to clock the ADS8325 after the
conversion is complete and to obtain the serial data
least significant bit first. See the Timing Information
section for more information.
NOTE: The maximum differential voltage between +IN and – IN of the ADS8325 is V
REF
. See Figure 28 for a further
explanation of the common-mode voltage range for differential inputs.
Figure 27. Differential Input Mode of the ADS8325
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