Datasheet

ADS8324
9
SBAS172A
www.ti.com
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
SMPL
Analog Input Sample Time 4.5 5.0 Clk Cycles
t
CONV
Conversion Time 16 Clk Cycles
t
CYC
Throughput Rate 50 kHz
t
CSD
CS Falling to 0 ns
DCLOCK LOW
t
SUCS
CS Falling to 50 ns
DCLOCK Rising
t
hDO
DCLOCK Falling to 5 20 ns
Current D
OUT
Not Valid
t
dDO
DCLOCK Falling to Next 100 250 ns
D
OUT
Valid
t
dis
CS Rising to D
OUT
Tri-State 50 100 ns
t
en
DCLOCK Falling to D
OUT
100 200 ns
Enabled
t
f
D
OUT
Fall Time 50 150 ns
t
r
D
OUT
Rise Time 75 200 ns
FIGURE 5. ADS8324 Basic Timing Diagrams.
DIGITAL INTERFACE
SIGNAL LEVELS
The CMOS digital output (D
OUT
) will swing from 0V to
V
CC
. If V
CC
is 3V, and this output is connected to a 5V
CMOS logic input, then that IC may require more supply
current than normal and may have a slightly longer propaga-
tion delay.
SERIAL INTERFACE
The ADS8324 communicates with microprocessors and
other digital systems via a synchronous 3-wire serial inter-
face, as shown in Figure 5 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for D
OUT
is acceptable,
the system can use the falling edge of DCLOCK to
capture each bit.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, D
OUT
is enabled and will output a LOW
value for one clock period. For the next 16 DCLOCK
periods, D
OUT
will output the conversion result, most sig-
nificant bit first followed by two zeros on clock cycles 15
and 16. After the two zero “dummy bits” have been output,
subsequent clocks will repeat the output data but in a least
significant bit first format starting with a zero.
CS must be taken HIGH following a conversion in order to
place DOUT in tri-state. Subsequent clocks will have no
effect on the converter. A new conversion is initiated only
when CS has been taken HIGH and returned LOW.
DATA FORMAT
The output data from the ADS8324 is in Binary Two’s
Complement format, as shown in Table II. This table repre-
sents the ideal output code for the given input voltage and
does not include the effects of offset, gain error, or noise.
TABLE I. Timing Specifications (V
CC
= 1.8V) –40°C to
+85°C.
See Figure 6 for test conditions.
CS/SHDN
D
OUT
DCLOCK
Complete Cycle
Power Down
ConversionSample
Use positive clock edge for data transfer
t
SUCS
t
CONV
t
SMPL
NOTE: Minimum 22 clock cycles required for 14-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
B13
(MSB)
B12 B11 B10 B9 B8 B7 B6 B0
(LSB)
00B5 B4 B3 B1B2
Hi-Z
0
Hi-Z
t
CSD
DESCRIPTION ANALOG VALUE
Full-Scale Range 2 • V
REF
Least Significant 2 • V
REF
/16384
Bit (LSB) BINARY CODE HEX CODE
+Full Scale +V
REF
– 1 LSB 0111 1111 1111 1100 7FFC
Midscale 0V 0000 0000 0000 0000 0000
Midscale – 1LSB 0V – 1 LSB 1111 1111 1111 1100 FFFC
–Full Scale –V
REF
1000 0000 0000 0000 8000
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
TABLE II. Ideal Input Voltages and Output Codes.