Datasheet

ADS8324
11
SBAS172A
www.ti.com
Figure 7 shows the current consumption of the ADS8324
versus sample rate. For this graph, the converter is clocked
at 1.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 8 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/24
th
of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
There is an important distinction between the power-down
mode that is entered after a conversion is complete and the
full power-down mode that is enabled when CS is HIGH. CS
LOW will shut down only the analog section. The digital
section is completely shutdown only when CS is HIGH.
Thus, if CS is left LOW at the end of a conversion and the
converter is continually clocked, the power consumption
will not be as low as when CS is HIGH, shown in Figure 9.
FIGURE 7. Maintaining f
CLK
at the Highest Possible Rate
Allows Supply Current to Drop Linearly with
Sample Rate.
FIGURE 8. Scaling f
CLK
Reduces Supply Current Only
Slightly with Sample Rate.
FIGURE 9. Shutdown Current with CS HIGH is 50nA
Typically, Regardless of the Clock. Shutdown
Current with CS LOW Varies with Sample
Rate.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8324 circuitry. This will be
particularly true if the reference voltage is low and/or the
conversion rate is high. At a 50kHz conversion rate, the
ADS8324 makes a bit decision every 213ns. That is, for each
subsequent bit decision, the digital output must be updated
with the results of the last bit decision, the capacitor array
appropriately switched and charged, and the input to the
comparator settled to a 14-bit level all within one clock
cycle.
The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during
any single conversion for an n-bit SAR converter, there are
n “windows” in which large external transient voltages can
easily affect the conversion result. Such spikes might origi-
nate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter’s DCLOCK signal—as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.
With this in mind, power to the ADS8324 should be clean
and well bypassed. A 0.1μF ceramic bypass capacitor should
be placed as close to the ADS8324 package as possible. In
addition, a 1μF to 10μF capacitor and a 5Ω or 10Ω series
resistor may be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1μF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the op
10000
1000
100
10
Supply Current (μA)
0.1 1 10 100
Sample Rate (kHz)
T
A
= 25°C
V
CC
= 1.8V
V
REF
= 0.9V
f
CLK
= 2.4MHz
10000
1000
100
10
Supply Current (μA)
0.1 1 10 100
Sample Rate (kHz)
T
A
= 25°C
V
CC
= 1.8V
V
REF
= 0.9V
f
CLK
= 24 • f
SAMPLE
10000
1000
800
600
400
200
0.250
0.00
Supply Current (μA)
0.1 1 10 100
Sample Rate (kHz)
T
A
= 25°C
V
CC
= 1.8V
V
REF
= 0.9V
f
CLK
= 24 • f
SAMPLE
CS LOW (GND)
CS HIGH (V
CC
)