Datasheet

1CLOCK
Acquisition
CONVST
BUSY
BYTE
CS
RD
DB15-D8
DB7-D0
2 3 4 5 17 18 19 20
3 41 2 17 18 19 20
t
C1
t
W1
t
D1
t
W3
t
W4
AcquisitionConversion
t
ACQ
t
CONV
t
D2
t
D4
t
W5
t
D5
t
D6
t
D3
t
D7
t
W6
t
D8
Bits15-8 Bits15-8 FF
t
D9
t
W7
t
W2
Bits7-0 Bits7-0 Bits15-8
ADS8323
www.ti.com SBAS224C –DECEMBER 2001–REVISED JANUARY 2010
TIMING INFORMATION
TIMING CHARACTERISTICS
(1)(2)
All specifications typical at –40°C to +85°C, +DV
DD
= +5V.
ADS8323
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
CONV
Conversion Time 1.6 μs
t
AQC
Acquisition Time 350 ns
t
C1
CLOCK Period 100 ns
t
W1
CLOCK High Time 40 ns
t
W2
CLOCK Low Time 40 ns
t
D1
CONVST Low to Clock High 10 ns
t
W3
CONVST Low Time 20 ns
t
D2
CONVST Low to BUSY High 25 ns
t
D3
CS Low to CONVST Low 0 ns
t
W4
CONVST High 20 ns
t
D4
CLOCK High to BUSY Low 25 ns
t
W5
CS High 0 ns
t
D5
CS Low to RD Low 0 ns
t
D6
RD High to CS High 0 ns
t
W6
RD Low Time 50 ns
t
D7
RD Low to Data Valid 40 ns
t
D8
Data Hold from RD High 5 ns
t
D9
BYTE Change to RD Low
(3)
0 ns
t
W7
RD High Time 20 ns
(1) All input signals are specified with rise and fall times of 5ns, t
R
= t
F
= 5ns (10% to 90% of DV
DD
) and timed from a voltage level of (V
IL
+
V
IH
) /2.
(2) See timing diagram.
(3) BYTE is asynchronous; when BYTE is '0', bits 15 through 0 appear at DB15-DB0. When BYTE is '1', bits 15 through 8 appear on
DB7-DB0. RD may remain low between changes in BYTE.
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