Datasheet

ADS8323
www.ti.com SBAS224C –DECEMBER 2001–REVISED JANUARY 2010
EXPLANATION OF CLOCK, BUSY AND BYTE
remain low without initiating a new conversion. The
PINS
CONVST signal must be high for at least 20ns (see
Timing Diagram, t
W4
) before it is brought low again
CLOCK: An external clock must be provided for the
and CONVST must stay low for at least 20ns (see
ADS8323. The maximum clock frequency is 10MHz
Timing Diagram, t
W3
). Once a CONVST signal goes
and that provides 500kSPS throughput. The minimum
low, further impulses of this signal are ignored until
clock frequency is 25kHz and that provides 1.25kHz
the conversion is finished or the device is reset.
throughput. The minimum clock cycle is 100ns (see
Timing Diagram, t
C1
), and CLOCK must remain high
When the conversion is finished (after 16 clock
(see Timing Diagram, t
W1
) or low (see Timing
cycles) the sampling switches close and sample the
Diagram, t
W2
) for at least 40ns.
new value. The start of the next conversion must be
delayed to allow the input capacitor of the ADS8323
BUSY: Initially, BUSY output is low. Reading data
to be fully charged. This delay time depends on the
from output register or sampling the input analog
driving amplifier, but should be at least 400ns. To
signal does not affect the state of the BUSY signal.
gain acquisition time, the falling edge of CONVST
After the CONVST input goes low and conversion
must take place just before the rising edge of CLOCK
starts, a maximum of 25ns later the BUSY output
(see Timing Diagram, t
D1
). One conversion cycle
goes high. That signal stays high during conversion
requires 20 clock cycles. However, reading data
and provides the status of the internal ADC to the
during the conversion or on a falling hold edge may
DSP or μC. At the end of conversion, on the rising
cause a loss in performance.
edge of the 17th clock cycle, new data from the
internal ADC are latched into the output registers.
Reading Data (RD, CS): In general, the data outputs
The BUSY signal goes low a maximum of 25ns later
are in 3-state. Both CS and RD must be low to
(see Timing Diagram, t
D4
).
enable these outputs. RD and CS must stay low
together for at least 40ns (see Timing Diagram, t
D7
)
BYTE: The output data appear as a full 16-bit word
before the output data is valid. RD must remain high
on DB15-DB0 (MSB-LSB or D15-D0) if BYTE is low.
for at least 20ns (see Timing Diagram, t
W7
) before
If there is only an 8-bit bus available on a board, the
bringing it back low for a subsequent read command.
result may also be read on an 8-bit bus by using only
16 clock-cycles after the start of a conversion (that is,
DB7-DB0. In this case, two reads are necessary (see
the next rising edge of the clock after the falling edge
the timing diagram). The first, as before, leaving
of CONVST), the new data are latched into the output
BYTE low and reading the eight least significant bits
register and the reading process can start again.
on DB7-DB0, then bringing BYTE high. When BYTE
Refer to Table 1 for ideal output codes.
is high, the upper eight bits (D15-D8) appear on
DB7-DB0.
CS being low tells the ADS8323 that the bus on the
board is assigned to the ADS8323. If an ADC shares
START OF A CONVERSION AND READING DATA
a bus with digital gates, there is a possibility that
digital (high-frequency) noise could get coupled into
By bringing the CONVST signal low, the input data
the ADC. If the bus is just used by the ADS8323, CS
are immediately placed in the hold mode (10ns),
can be hard-wired to ground. The output data should
although CS must be low when CONVST goes low to
not be read 125ns prior to the falling edge of
initiate a conversion. The conversion follows with the
CONVST and 10ns after the falling edge.
next rising edge of CLOCK. If it is important to detect
a hold command during a certain clock cycle, then
The ADS8323 output is in binary twos complement
the falling edge of the CONVST signal must occur at
format (see Figure 22).
least 10ns before the rising edge of CLOCK (see
Timing Diagram, t
D1
). The CONVST signal can
Table 1. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT
DESCRIPTION ANALOG VALUE BINARY TWOS COMPLEMENT
Full-Scale Range 2 • V
REF
Least Significant Bit (LSB) 2 • V
REF
/65535 BINARY CODE HEX CODE
+Full Scale +V
REF
– 1 LSB 0111 1111 1111 1111 7FFF
Midscale 0V 0000 0000 0000 0000 0000
Midscale – 1 LSB 0V – 1 LSB 1111 1111 1111 1111 FFFF
Zero –V
REF
1000 0000 0000 0000 8000
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