Datasheet

R
1
R
2
+IN(pin26)
-IN(pin25)
REF (pin32)
OUT
2.5V
4kW
20kW
OPA132
ADS8323
OPA353
Bipolar
Input
±
±
±
10V 1k 5k
5V 2k 10k
2.5V 4k 20k
W W
W W
W W
BIPOLARINPUT
R
1
R
2
54
300
5052
1968
818
0014 0015 0017 00180016
Code
ADS8323
SBAS224C –DECEMBER 2001–REVISED JANUARY 2010 www.ti.com
NOISE
Figure 20 shows the transition noise of the ADS8323.
A low-level dc input was applied to the analog-input
pins and the converter was put through 8192
conversions. The digital output of the ADC varies in
output code due to the internal noise of the ADS8323.
This characteristic is true for all 16-bit SAR-type
ADCs. The ADS8323, with five output codes for the σ
distribution, yields a greater than ±0.8LSB transition
noise at 5V operation. Remember that to achieve this
low-noise performance, the peak-to-peak noise of the
input signal and reference must be less than 50μV.
Figure 21. Level Shift Circuit for Bipolar Input
Ranges
DIGITAL INTERFACE
TIMING AND CONTROL
See the timing diagram and the Timing
Characteristics section for detailed information on
timing signals and the respective requirements for
each.
Figure 20. Histogram of 8,192 Conversions of a
The ADS8323 uses an external clock (CLOCK, pin
Low-Level DC Input
20) that controls the conversion rate of the CDAC.
With a 10MHz external clock, the ADC sampling rate
is 500kSPS that corresponds to a 2μs maximum
AVERAGING
throughput time.
Averaging the digital codes can compensate the
Conversions are initiated by bringing the CONVST
noise of the ADC. By averaging conversion results,
pin low for a minimum of 20ns (after the 20ns
transition noise is reduced by a factor of 1/√n, where
minimum requirement has been met, the CONVST
n is the number of averages. For example, averaging
pin can be brought high), while CS is low. The
four conversion results reduces the transition noise
ADS8322 switches from Sample-to-Hold mode on the
by 1/2 to ±0.4LSB. Averaging should only be used for
falling edge of the CONVST command. Following the
input signals with frequencies near dc. For ac signals,
first rising edge of the external clock after a CONVST
a digital filter can be used to low-pass filter and
low, the ADS8322 begins conversion (this first rising
decimate the output codes. This process works in a
edge of the external clock represents the start of
similar manner to averaging—for every decimation by
clock cycle one; the ADS8322 requires 16 rising clock
2, the signal-to-noise ratio improves by 3dB.
edges to complete a conversion). The BUSY output
goes high immediately following CONVST going low.
BIPOLAR INPUTS
BUSY stays high through the conversion process and
returns low when the conversion has ended.
The differential inputs of the ADS8323 were designed
to accept bipolar inputs (–V
REF
and +V
REF
) around the
Both RD and CS can be high during and before a
common-mode voltage, which corresponds to a 0V to
conversion (although CS must be low when CONVST
5V input range with a 2.5V reference. By using a
goes low to initiate a conversion). Both the RD and
simple op amp circuit featuring four high-precision
CS pins are brought low in order to enable the
external resistors, the ADS8323 can be configured to
parallel output bus with the conversion.
accept bipolar inputs. The conventional ±2.5V, ±5V,
and ±10V input ranges could be interfaced to the
ADS8323 using the resistor values shown in
Figure 21.
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