Datasheet

ADS8323
ADS8323
-V to+V
peak-to-peak
REF REF
V
peak-to-peak
REF
V
peak-to-peak
REF
Common
Voltage
Common
Voltage
Single-EndedInput
DifferentialInput
ADS8323
SBAS224C –DECEMBER 2001–REVISED JANUARY 2010 www.ti.com
The analog input is provided to two input pins, +IN delta of repeated aperture delay values is typically
and –IN. When a conversion is initiated, the 30ps (also known as aperture jitter). These
differential input on these pins is sampled on the specifications reflect the ability of the ADS8323 to
internal capacitor array. A conversion is initiated on capture ac input signals accurately at the exact same
the ADS8323 by bringing CONVST (pin 21) low for a moment in time.
minimum of 20ns. CONVST low places the
sample-and-hold amplifier in the hold state and the
REFERENCE
conversion process is started. The BUSY output (pin
If the internal reference is used, REF
OUT
(pin 32)
17) goes high when the conversion begins and stays
should be directly connected to REF
IN
(pin 31); see
high during the conversion. While a conversion is in
Figure 15. The ADS8323 can operate, however, with
progress, both inputs are disconnected from any
an external reference in the range of 1.5V to 2.55V
internal function. When the conversion result is
for a corresponding full-scale range of 3.0V to 5.1V.
latched into the output register, the BUSY signal goes
The internal reference of the ADS8323 is
low. The data can be read from the parallel output
double-buffered. If the internal reference is used to
bus following the conversion by bringing both RD and
drive an external load, a buffer is provided between
CS low.
the reference and the load applied to REF
OUT
(pin 32)
NOTE: This mode of operation is described in more
(the internal reference can typically source or sink
detail in the Timing and Control section of this data
10μA of current; compensation capacitance should be
sheet.
at least 0.1μF to minimize noise). If an external
reference is used, the second buffer provides
SAMPLE-AND-HOLD SECTION isolation between the external reference and the
CDAC. This buffer is also used to recharge all of the
The sample-and-hold on the ADS8323 allows the
capacitors of the CDAC during conversion.
ADC to accurately convert an input sine wave of
full-scale amplitude to 16-bit resolution. The input
ANALOG INPUT
bandwidth of the sample-and-hold is greater than the
Nyquist rate (Nyquist equals one-half of the sampling
The analog input is bipolar and fully differential. There
rate) of the ADC even when the ADC is operated at
are two general methods of driving the analog input
its maximum throughput rate of 500kSPS. The typical
of the ADS8323: single-ended or differential, as
small-signal bandwidth of the sample-and-hold
shown in Figure 16 and Figure 17. When the input is
amplifier is 20MHz. The typical aperture delay time,
single-ended, the –IN input is held at the
or the time it takes for the ADS8323 to switch from
common-mode voltage. The +IN input swings around
the sample to the hold mode following the negative
the same common voltage and the peak-to-peak
edge of the CONVST signal, is 10ns. The average
amplitude is the (common-mode + V
REF
) and the
(common-mode – V
REF
). The value of V
REF
determines the range over which the common-mode
voltage may vary (see Figure 18).
Figure 16. Methods of Driving the ADS8323: Single-Ended or Differential
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