Datasheet

DB6 DB5 DB4 DB3 DB2 DB1 DB0
NC NC
+AV
DD
AGND
+IN
-IN
REF
OUT
REF
IN
-
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CS
BYTE
RD
CONVST
CLOCK
DGND
+DV
DD
BUSY
DB7
ChipSelect
ReadInput
ConversionStart
ClockInput
BusyOutput
+
AnalogInput
9 10
11 12
13
14
15 16
32 31 30 29 28
ADS8322
27 26 25
0.1mF
10mF
+5VAnalogSupply
+
0.1mF
ADS8323
www.ti.com SBAS224C –DECEMBER 2001–REVISED JANUARY 2010
THEORY OF OPERATION
The ADS8322 is a high-speed successive
The ADS8323 requires an external clock to run the
approximation register (SAR) A/D converter with an
conversion process. This clock can vary between
internal 2.5V bandgap reference that operates from a
25kHz (1.25kHz throughput) and 10MHz (500kSPS
single +5V supply. The input is fully differential with a
throughput). The duty cycle of the clock is
typical common-mode rejection of 70dB. The device
unimportant as long as the minimum high and low
accepts a differential analog input voltage in the
times are at least 40ns and the clock period is at
range of –V
REF
to +V
REF
, centered on the
least 100ns. The minimum clock frequency is
common-mode voltage (see the Analog Input
governed by the parasitic leakage of the Capacitive
section). The device also accepts bipolar input ranges
Digital-to-Analog Converter (CDAC) capacitors
when a level shift circuit is used at the front end (see
internal to the ADS8323.
Figure 21). The basic operating circuit for the
ADS8323 is shown in Figure 15.
white space here
Figure 15. Typical Circuit Configuration
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