Datasheet

1CLOCK
Acquisition
CONVST
BUSY
BYTE
CS
RD
DB15-D8
DB7-D0
2 3 4 5 17 18 19 20
3 41 2 17 18 19 20
t
1
t
2
t
4
t
6
t
9
AcquisitionConversion
t
ACQ
t
CONV
t
5
t
7
t
11
t
10
t
12
t
13
t
14
t
8
t
16
t
15
t
17
Bits15-8 Bits15-8 FF
t
18
t
19
t
3
Bits7-0 Bits7-0 Bits15-8
ADS8322
SBAS215A –JULY 2001–REVISED JANUARY 2010 www.ti.com
TIMING INFORMATION
TIMING CHARACTERISTICS
(1)(2)
All specifications typical at –40°C to +85°C, +V
D
= +5V.
ADS8322
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
CONV
Conversion Time 1.6 μs
t
AQC
Acquisition Time 350 ns
t
1
CLOCK Period 100 ns
t
2
CLOCK High Time 40 ns
t
3
CLOCK Low Time 40 ns
t
4
CONVST Low to Clock High 10 ns
t
5
CLOCK High to CONVST High 5 ns
t
6
CONVST Low Time 20 ns
t
7
CONVST Low to BUSY High 25 ns
t
8
CS Low to CONVST Low 0 ns
t
9
CONVST High 20 ns
t
10
CLOCK Low to CONVST Low 0 ns
t
11
CLOCK High to BUSY Low 25 ns
t
12
CS High 0 ns
t
13
CS Low to RD Low 0 ns
t
14
RD High to CS High 0 ns
t
15
RD Low Time 50 ns
t
16
RD Low to Data Valid 40 ns
t
17
Data Hold from RD High 5 ns
t
18
BYTE Change to RD Low
(3)
0 ns
t
19
RD High Time 20 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
) /2.
(2) See timing diagram, above.
(3) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BUSY is 1, bits 15 through 8 appear on
DB7-DB0. RD may remain low between changes in BYTE.
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