Datasheet

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Code
ADS8322
www.ti.com SBAS215A –JULY 2001–REVISED JANUARY 2010
BYTE AVERAGING
The output data appear as a full 16-bit word on The noise of the A/D converter can be compensated
DB15- DB0 (MSB-LSB), if BYTE is low. The result by averaging the digital codes. By averaging
may also be read on an 8-bit bus by using only conversion results, transition noise is reduced by a
DB7-DB0. In this case two reads are necessary. The factor of 1/√n, where n is the number of averages.
first read proceeds as before, leaving BYTE low and For example, averaging four conversion results
reading the eight least significant bits on DB7-DB0, reduces the transition noise by 1/2 to ±0.25 LSBs.
then bringing BYTE high. When BYTE is high, the Averaging should only be used for input signals with
upper eight bits (D15-D8) appear on DB7-DB0. frequencies near dc.
For ac signals, a digital filter can be used to low-pass
NOISE
filter and decimate the output codes. This
configuration works in a similar manner to averaging:
Figure 14 shows the transition noise of the ADS8322.
for every decimation by 2, the signal-to-noise ratio
A low-level dc input was applied to the analog input
improves by 3dB.
pins and the converter was put through 8,192
conversions. The digital output of the A/D converter
varies in output code due to the internal noise of the LAYOUT
ADS8322. This characteristic is true for all 16-bit
For optimum performance, care should be taken with
SAR-type A/D converters. Using a histogram to plot
the physical layout of the ADS8322 circuitry. This
the output codes, the distribution should appear
consideration is particularly true if the CLOCK input is
bell-shaped, with the peak of the bell curve
approaching the maximum throughput rate.
representing the nominal code for the input value.
The ±1σ, ±2σ, and ±3σ distributions respectively
As the ADS8322 offers single-supply operation, it is
represent the 68.3%, 95.5%, and 99.7% of all codes.
often used in close proximity with digital logic,
The transition noise can be calculated by dividing the
microcontrollers, microprocessors, and digital signal
number of codes measured by six; this yields the ±3σ
processors. The more digital logic present in the
distribution, or 99.7%, of all codes. Statistically, up to
design and the higher the switching speed, the more
three codes could fall outside the distribution when
difficult it is to achieve good performance from the
executing 1,000 conversions. The ADS8322, with five
converter.
output codes for the ±3σ distribution, yields a <
The basic SAR architecture is sensitive to glitches or
±0.8LSB transition noise at 5V operation. Remember
sudden changes on the power supply, reference,
that to achieve this low-noise performance, the
ground connections and digital inputs that occur just
peak-to-peak noise of the input signal and reference
before latching the output of the analog comparator.
must be < 50μV.
Thus, during any single conversion for an n-bit SAR
converter, there are n windows in which large
external transient voltages can affect the conversion
result. Such glitches might originate from switching
power supplies, or nearby digital logic or high-power
devices.
The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of
the external event. These errors can change if the
external event changes in time with respect to the
CLOCK input.
On average, the ADS8322 draws very little current
from an external reference, as the reference voltage
is internally buffered. If the reference voltage is
external and originates from an op amp, make sure
Figure 14. Histogram of 8,192 Conversions of a
that it can drive the bypass capacitor or capacitors
Low-Level DC Input
without oscillation.
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