Datasheet

ADS8322
SBAS215A –JULY 2001–REVISED JANUARY 2010 www.ti.com
REFERENCE The ADS8322 uses an external clock (CLOCK) which
controls the conversion rate of the CDAC. With a
Under normal operation, the REF
OUT
pin should be
10MHz external clock, the A/D converter sampling
directly connected to the REF
IN
pin to provide an
rate is 500kHz, which corresponds to a 2μs maximum
internal +2.5V reference to the ADS8322. The
throughput time.
ADS8322 can operate, however, with an external
reference in the range of 1.5V to 2.6V for a Conversions are initiated by bringing the CONVST
corresponding full-scale range of 3.0V to 5.2V. pin low for a minimum of 20ns (after the 20ns
minimum requirement has been met, the CONVST
The internal reference of the ADS8322 is
pin can be brought high), while CS is low. The
double-buffered. If the internal reference is used to
ADS8322 switches from Sample-to-Hold mode on the
drive an external load, a buffer is provided between
falling edge of the CONVST command. Following the
the reference and the load applied to the REF
OUT
pin
first rising edge of the external clock after a CONVST
(the internal reference can typically source and sink
low, the ADS8322 begins conversion (this first rising
10μA of current). If an external reference is used, the
edge of the external clock represents the start of
second buffer provides isolation between the external
clock cycle one; the ADS8322 requires 16 rising clock
reference and the CDAC. This buffer is also used to
edges to complete a conversion). The BUSY output
recharge all of the CDAC capacitors during
goes high immediately following CONVST going low.
conversion.
BUSY stays high through the conversion process and
returns low when the conversion has ended.
ANALOG INPUT
Both RD and CS can be high during and before a
When the converter enters the Hold mode, the
conversion (although CS must be low when CONVST
voltage difference between the +IN and –IN inputs is
goes low to initiate a conversion). Both the RD and
captured on the internal capacitor array. The voltage
CS pins are brought low in order to enable the
on the –IN input is limited between –0.1V and 0.5V,
parallel output bus with the conversion.
allowing the input to reject small signals which are
common to both the +IN and –IN inputs. The +IN
READING DATA
input has a range of –0.1V to +V
A
+ 0.1V.
The ADS8322 outputs full parallel data in Straight
The input current on the analog inputs depends upon
Binary format, as shown in Table 1. The parallel
a number of factors: sample rate, input voltage, and
output is active when CS and RD are both LOW. The
source impedance. Essentially, the current into the
output data should not be read 125ns before the
ADS8322 charges the internal capacitor array during
falling edge of CONVST and 10ns after the falling
the sample period. After this capacitance has been
edge. Any other combination of CS and RD will
fully charged, there is no further input current. The
3-state the parallel output. Refer to Table 1 for ideal
source of the analog input voltage must be able to
output codes.
charge the input capacitance (25pF) to a 16-bit
settling level within the acquisition time (400ns) of the
Table 1. Ideal Input Voltages and Output Codes
device. When the converter goes into Hold mode, the
ANALOG DIGITAL OUTPUT
input impedance is greater than 1GΩ.
DESCRIPTION VALUE STRAIGHT BINARY
Care must be taken regarding the absolute analog
Full-Scale
2 • V
REF
input voltage. To maintain the linearity of the
Range
converter, the –IN input should not drop below GND –
Least Significant 2 • BINARY
100mV or exceed GND + 0.5V. The +IN input should
Bit (LSB) V
REF
/65535 CODE HEX CODE
always remain within the range of GND – 100mV to
2V
REF
– 1 1111 1111
+Full Scale FFFF
V
A
+ 100mV. Outside of these ranges, the converter
LSB 1111 1111
linearity may not meet specifications. To minimize
1000 0000
Midscale V
REF
8000
noise, low-bandwidth input signals with low-pass
0000 0000
filters should be used.
0111 1111
Midscale – LSB V
REF
– 1 LSB 7FFF
1111 1111
DIGITAL INTERFACE
0000 0000
Zero 0 0000
0000 0000
TIMING AND CONTROL
See the timing diagram and the Timing
Characteristics section for detailed information on
timing signals and the respective requirements for
each.
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