Datasheet

ADS8321
3
SBAS123B
www.ti.com
SPECIFICATIONS: +V
CC
= +5V
At 40°C to +85°C, V
REF
= +2.5V, In = 2.5V, f
SAMPLE
= 100kHz, and f
CLK
= 24 f
SAMPLE
, unless otherwise specified.
ADS8321E ADS8321EB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 Bits
ANALOG INPUT
Full-Scale Input Span +In (In) V
REF
+V
REF
✻✻V
Absolute Input Range +In 0.1
V
CC
+ 0.1
✻✻V
In 0.1 +4.0 ✻✻V
Capacitance 25 pF
Leakage Current 1 nA
SYSTEM PERFORMANCE
No Missing Codes 14 15 Bits
Integral Linearity Error ±0.008 ±0.018 ±0.006 ±0.012
% of FSR
Offset Error ±0.4 ±2 ±0.2 ±1mV
Offset Temperature Drift ±1 µV/°C
Gain Error, Positive ±0.05 ±0.024 %
Negative ±0.05 ±0.024 %
Gain Temperature Drift ±0.3 ppm/°C
Noise 60 µVrms
Common-Mode Rejection Ratio 80 dB
Power Supply Rejection Ratio +4.7V < V
CC
< 5.25V 3 LSB
(1)
SAMPLING DYNAMICS
Conversion Time 16
Clk Cycles
Acquisition Time 4.5
Clk Cycles
Throughput Rate 100 kHz
Clock Frequency Range 0.024 2.9 ✻✻MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion V
IN
= 5Vp-p at 10kHz 84 86 dB
SINAD V
IN
= 5Vp-p at 10kHz 82 84 dB
Spurious Free Dynamic Range V
IN
= 5Vp-p at 10kHz 84 86 dB
SNR 85 87 dB
REFERENCE INPUT
Voltage Range 0.5 V
CC
/2 ✻✻V
Resistance
CS = GND, f
SAMPLE
= 0Hz
5 G
CS = V
CC
5 G
Current Drain 40 80 ✻✻µA
f
SAMPLE
= 10kHz 0.8 µA
CS = V
CC
0.1
3
µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Levels:
V
IH
I
IH
= +5µA 3.0
V
CC
+ 0.3
✻✻V
V
IL
I
IL
= +5µA 0.3 0.8 ✻✻V
V
OH
I
OH
= 250µA 4.0 V
V
OL
I
OL
= 250µA 0.4 V
Data Format
POWER SUPPLY REQUIREMENTS
V
CC
Specified Performance 4.75 5.25 ✻✻V
V
CC
Range
(2)
2.7 5.25 ✻✻V
Quiescent Current 1100 1700 ✻✻µA
f
SAMPLE
= 10kHz
(3, 4)
250 µA
Power Dissipation 5.5 8.5 ✻✻mW
Power Down CS = V
CC
0.3 3 ✻✻µA
TEMPERATURE RANGE
Specified Performance 40 +85 ✻✻°C
Specifications same as ADS8321E.
NOTES: (1) LSB means Least Significant Bit. (2) See Typical Performance Curves for more information. (3) f
CLK
= 2.4MHz, CS = V
CC
for 216 clock cycles out
of every 240. (4) See the Power Dissipation section for more information regarding lower sample rates.
Binary Twos Complement